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參數(shù)資料
| 型號(hào)： | AD8099ACPZ-R2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Ultralow Distortion, High Speed 0.95 nV/Hz Voltage Noise Op Amp |
| 中文描述： | OP-AMP, 500 uV OFFSET-MAX, PDSO8 |
| 封裝： | 3 X 3 MM, LEAD FREE, PLASTIC, LFCSP-8 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 1208K |
| 代理商： | AD8099ACPZ-R2 |
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AD8099
Rev. B | Page 21 of 28
0
"GAIN FROM
R1
"GAIN FROM
NOISE GAIN =
NG = 1 +R1
I
N–
V
N
V
N, R1
V
N, R3
R1
R2
I
N+
R3
4kTR2
4kTR1
4kTR3
V
N, R2
B
A
V
N2
+ 4kTR3 + 4kTR1 R1 + R2
2
I
N+2
R3
2
+ I
N–2
R1 × R2
2
+ 4kTR2
R1
2
R1 + R2
R1 + R2
RTI NOISE =
RTO NOISE = NG × RTI NOISE
V
OUT
+
Figure 69. Op Amp Noise Analysis Model
In applications where noise sensitivity is critical, care must be
taken not to introduce other significant noise sources to the
amplifier. Each resistor is a noise source. Attention to the
following areas is critical to maintain low noise performance:
design, layout, and component selection. A summary of noise
performance for the amplifier and associated resistors can be
seen in Table 4.
INPUT BIAS CURRENT AND DC OFFSET
In high noise gain configurations, the effects of output offset
voltage can be significant, even with low input bias currents and
input offset voltages. Figure 70 shows a comprehensive offset
voltage model, which can be used to determine the referred to
output (RTO) offset voltage of the amplifier or referred to input
(RTI) offset voltage.
0
"GAIN FROM
R1
"GAIN FROM
NOISE GAIN =
NG = 1 +R1
I
B–
V
OS
R1
R2
I
B+
R3
B
A
OFFSET (RTO) = V
OS
1 +R1
B+
× R3 1 +R1
– I
B–
× R2
OFFSET (RTI) = V
OS
+ I
B+
× R3 – I
B–
R1 × R2
R1 + R2
OFFSET (RTI) = V
OS
IF I
B+
= I
B–
AND R3 =
R1 × R2
R1 + R2
V
OUT
FOR BIAS CURRENT CANCELLATION:
Figure 70. Op Amp Total Offset Voltage Model
For RTO calculations, the input offset voltage and the voltage
generated by the bias current flowing through R3 are multiplied
by the noise gain of the amplifier. The voltage generated by I
B–
through R2 is summed together with the previous offset
voltages to arrive at a final output offset voltage. The offset
voltage can also be referred to the input (RTI) by dividing the
calculated output offset voltage by the noise gain.
As seen in Figure 70 if I
B+
and I
B–
are the same and R3 equals the
parallel combination of R1 and R2, then the RTI offset voltage
can be reduced to only V
OS.
This is a common method used to
reduce output offset voltage. Keeping resistances low helps to
minimize offset error voltage and keeps the voltage noise low.
DISABLE PIN AND INPUT BIAS CANCELLATION
The AD8099 DISABLE pin performs three functions; enable,
disable, and reduction of the input bias current. When the
DISABLE pin is brought to within 0.7 V of the positive supply,
the input bias current is reduced by an approximate factor of 60.
However, the input current noise doubles to 5.2 pA/
√
Hz. Table
5 outlines the DISABLE pin functionality.
Table 5. DISABLE Pin Truth Table
Supply Voltage
Disable
Enable
Low Input Bias Current
±5 V
–5 to +2.4
Open
4.3 to 5
+5 V
0 to 2.4
Open
4.3 to 5
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