參數(shù)資料
型號: AD8072JRZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 2/13頁
文件大小: 0K
描述: IC VIDEO AMP DUAL 8-SOIC T/R
標準包裝: 1,000
應用: 電流反饋
電路數(shù): 2
-3db帶寬: 100MHz
轉換速率: 500 V/µs
電流 - 電源: 3.5mA
電流 - 輸出 / 通道: 30mA
電壓 - 電源,單路/雙路(±): 5 V ~ 12 V,±2.5 V ~ 6 V
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 帶卷 (TR)
REV. D
AD8072/AD8073
–9–
APPLICATIONS
Overdrive Recovery
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this overdrive
condition and resume normal operation. As shown in Figure 4,
the AD8072 and AD8073 recover within 75 ns from positive
overdrive and 30 ns from negative overdrive.
25ns
1V
VIN
VOUT
Figure 4. Overload Recovery; VS =
±5 V, VIN = 8 V p-p,
RF = 1 k
, RL = 150 , G = +2
Bandwidth vs. Feedback Resistor Value
The closed-loop frequency response of a current feedback amplifier
is a function of the feedback resistor. A smaller feedback resistor
will produce a wider bandwidth response. However, if the feed-
back resistance becomes too small, the gain flatness can be
affected. As a practical consideration, the minimum value of
feedback resistance for the AD8072/AD8073 was found to be
649
. For resistances below this value, the gain flatness will be
affected and more significant lot-to-lot variations in device per-
formance will be noticed. Figure 5 shows a plot of the frequency
response of an AD8072/AD8073 at a gain of two with both feed-
back and gain resistors equal to 649
.
FREQUENCY – MHz
6.1
GAIN
FLATNESS
dB
6.0
0.1
500
1
10
100
5.9
5.8
5.4
5.7
5.6
5.5
RF = 2k
RF = 649
1 dB
DIV
0.1 dB
DIV
6
7
5
4
3
2
1
0
VS = 5V
AV = 2
RL = 150
VO = 0.2V p-p
CLOSED-LOOP
GAIN
dB
Figure 5. Frequency Response vs. RF
On the other hand, the bandwidth of a current feedback ampli-
fier can be decreased by increasing the feedback resistance. This
can sometimes be useful where it is desired to reduce the noise
bandwidth of a system. As a practical matter, the maximum
value of feedback resistor was found to be 2 k
. Figure 5 shows
the frequency response of an AD8072/AD8073 at a gain of two
with both feedback and gain resistors equal to 2 k
.
Capacitive Load Drive
When an op amp output drives a capacitive load, extra phase shift
due to the pole formed by the op amp’s output impedance and
the capacitor can cause peaking or even oscillation. The top trace
of Figure 6, RS = 0
, shows the output of one of the amplifiers of
the AD8072/AD8073 when driving a 50 pF capacitor as shown in
the schematic of Figure 7.
The amount of peaking can be significantly reduced by adding
a resistor in series with the capacitor. The lower trace of Figure 6
shows the same capacitor being driven with a 25
resistor
in series with it. In general, the resistor value will have to be
experimentally determined, but 10
to 50 is a practical range
of values to experiment with for capacitive loads of up to a few
hundred pF.
20ns
50mV
RS = 0
RS = 25
Figure 6. Capacitive Low Drive
1k
50
VIN = 100mV p-p
RL
1k
CL
50pF
RS
Figure 7. Capacitive Load Drive Circuit
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