- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375241 > AD802 (Analog Devices, Inc.) Clock Recovery and Data Retiming Phase-Locked Loop(時(shí)鐘恢復(fù)和重定時(shí)PLL) PDF資料下載
參數(shù)資料
| 型號(hào)： | AD802 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Clock Recovery and Data Retiming Phase-Locked Loop(時(shí)鐘恢復(fù)和重定時(shí)PLL) |
| 中文描述： | 時(shí)鐘恢復(fù)和數(shù)據(jù)重定時(shí)鎖相環(huán)（時(shí)鐘恢復(fù)和重定時(shí)鎖相環(huán)） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 258K |
| 代理商： | AD802 |
AD800/AD802
REV. B
–9–
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DATAOUT
DATAOUT
V
CC2
CLKOUT
CLKOUT
AV
EE
ASUBST
FRAC
FRAC
SUBST
DATAIN
DATAIN
AV
CC
CF
1
CF
2
DATAOUT
DATAOUT
CLKOUT
CLKOUT
Z1
AD800/802
J1
J2
R1
100
R2
100
R5 100
R10
154
R6 100
5.0V
R9
R12
154
R11
154
R7 100
R8 100
R3
100
R4
100
J3
J4
C10
0.1
C
D
R22
80.6
R21
80.6
R19
130
R20
130
FRAC
FRAC
5.0V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Z2
10H116
R24
130
R23
130
J5
J6
80.6
R25
80.6
DATAIN
DATAIN
5.0V
0.1
0.1
0.1
C7 0.1
C6 0.1
0.1
C16
5.0V
5.0V
R16 100
5.0V
C13 0.1
100
C14 0.1
100
154
154
0.1
C20
0.1
C21 0.1
5.0V
5.0V
C8
C9
0.1
C5
C4
C3
R13
R14
R15 100
R17
R18
C17 0.1
C15 0.1
0.1
C12
C11
C19
V
EE
C2
10
μ
F
5.0V
BYPASS
NETWORK
OUT
IN
V
EE
V
CC1
V
EE
V
CC1
Figure 22. Evaluation Board Schematic, Positive Supply
T able I. E valuation Board, Positive Supply: Components List
Reference
Designator
Description
Quantity
R1–8, R15–18
R9–14
R19, 20, 23, 24
R21, 22, 25, 26
C
D
C2
C3–C21
Z1
Z2
Resistor, 100
, 1%
Resistor, 154
, 1%
Resistor, 130
, 1%
Resistor, 80.6
, 1%
Capacitor, Loop Damping (See Specifications Page)
Capacitor, 10
μ
F, T antalum
Capacitor, 0.1
μ
F, Ceramic Chip
AD800/AD802
10H116, ECL Line Receiver
12
6
4
4
1
1
17
1
1
IN
0.1
μ
F
C2
10
μ
F
BYPASS
NETWORK
(A, B, C,
OR D)
TO DEVICE
IN
5.0V
BEADS WITH ONE LOOP
IN
0.1
μ
F
TO
DEVICE
TO
DEVICE
(A)
IN
0.1
μ
F
TO
DEVICE
BEAD WITH
ONE LOOP
(B)
(C)
BEAD WITH
TWO LOOPS
IN
0.1
μ
F
TO
DEVICE
BEAD WITH
TWO LOOPS
(D)
BEAD WITH
TWO LOOPS
BYPASS NETWORK
COMPONENTS:
CAPACITOR ..........CERAMIC CHIP
FERRITE BEAD......1/4 IN. STACKPOLE CARBO 57-1392
3.0
0
1.0
1.5
0.5
0.1
1.0
0
2.5
2.0
0.9
0.7
0.6
0.5
0.8
0.4
0.3
0.2
J
NOISE – V p-p @ 311MHz
(A)
(B)
(C)
(D)
Figure 23. Bypass Network Schemes
Figure 24. AD802-155 Output J itter vs. Supply Noise
(PECL Configuration)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8013 | Single Supply Low Power,Triple Video Amplifier(單電源,低功耗,三通道視頻放大器) |
| AD8014 | 400 MHz Low Power High Performance Amplifier |
| AD8021ARMZ | Low Noise, High Speed Amplifier for 16-Bit Systems |
| AD8021ARMZ-REEL | Low Noise, High Speed Amplifier for 16-Bit Systems |
| AD8021ARMZ-REEL7 | Low Noise, High Speed Amplifier for 16-Bit Systems |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD80201Z | 制造商:Analog Devices 功能描述: |
| AD80206ABCPZ-125 | 制造商:Analog Devices 功能描述:ANAAD80206ABCPZ-125 14BIT IF DIVERSITY R |
| AD8021 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface |
| AD8021_06 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Noise, High Speed Amplifier for 16-Bit Systems |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。