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參數(shù)資料
| 型號： | AD802 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Clock Recovery and Data Retiming Phase-Locked Loop(時鐘恢復和重定時PLL) |
| 中文描述： | 時鐘恢復和數(shù)據(jù)重定時鎖相環(huán)（時鐘恢復和重定時鎖相環(huán)） |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 258K |
| 代理商： | AD802 |
AD800/AD802
REV. B
–3–
ABSOLUT E MAX IMUM RAT INGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
Input Voltage (Pin 16 or Pin 17 to V
CC
) . . . . V
EE
to +300 mV
Maximum Junction T emperature
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150
°
C
Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . +175
°
C
Storage T emperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Lead T emperature Range (Soldering 60 sec) . . . . . . . +300
°
C
ESD Rating
AD800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
AD802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to an absolute
maximum rating condition for an extended period may adversely affect device
reliability.
RECOVERED CLOCK
SKEW,
RCS
DATAO(PIN 2)
CLKO(PIN 5)
SETUP TIME
SU
Figure 1. Recovered Clock Skew and Setup
(See Previous Page)
PIN DE SCRIPT IONS
Number
Mnemonic
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
DATAOUT
DAT AOUT
V
CC2
CLKOUT
CLK OUT
V
EE
V
EE
V
CC1
AV
EE
ASUBST
CF
2
CF
1
AV
CC
V
CC1
V
EE
DAT AIN
DATAIN
SUBST
FRAC
Differential Retimed Data Output
Differential Retimed Data Output
Digital Ground
Differential Recovered Clock Output
Differential Recovered Clock Output
Digital V
EE
Digital V
EE
Digital Ground
Analog V
EE
Analog Substrate
Loop Damping Capacitor Input
Loop Damping Capacitor Input
Analog Ground
Digital Ground
Digital V
EE
Differential Data Input
Differential Data Input
Digital Substrate
Differential Frequency Acquisition
Indicator Output
Differential Frequency Acquisition
Indicator Output
20
FRAC
T HE RMAL CHARACT E RIST ICS
θ
JC
θ
JA
SOIC Package
Cerdip Package
22
°
C/W
25
°
C/W
75
°
C/W
90
°
C/W
Use of a heatsink may be required depending on operating
environment.
GLOSSARY
Maximum and Minimum Specifications
Maximum and minimum specifications result from statistical
analyses of measurements on multiple devices and multiple test
systems. T ypical specifications indicate mean measurements.
Maximum and minimum specifications are calculated by adding
or subtracting an appropriate guardband from the typical
specification. Device-to-device performance variation and test
system-to-test system variation contribute to each guardband.
Nominal Center Frequency
T his is the frequency that the VCO will operate at with no input
signal present and the loop damping capacitor, C
D
, shorted.
T racking Range
T his is the range of input data rates over which the PLL will
remain in lock.
Capture Range
T his is the range of input data rates over which the PLL can
acquire lock.
Static Phase E rror
T his is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling
instant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error, and IC input and output signals
prohibit direct measurement of static phase error.
Data T ransition Density,
r
T his is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods.
ρ
is the ratio
(0
≤
ρ
≤
1) of data transitions to clock periods.
Jitter
T his is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms, or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.
Output Jitter
T his is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some psuedo-random input data sequence
(PRN Sequence).
Jitter T olerance
Jitter tolerance is a measure of the PLL’s ability to track a jittery
input data signal. Jitter on the input data is best thought of as
phase modulation, and is usually specified in unit intervals.
ORDE RING GUIDE
Fractional Loop
Bandwidth
Device
Center Frequency
Description
Operating T emperature
Package Option
AD800-45BQ
AD800-52BR
AD802-155BR
AD802-155K R
44.736 MHz
51.84 MHz
155.52 MHz
155.52 MHz
0.1%
0.1%
0.08%
0.08%
20-Pin Cerdip
20-Pin Plastic SOIC
20-Pin Plastic SOIC
20-Pin Plastic SOIC
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
0
°
C to +70
°
C
Q-20
R-20
R-20
R-20
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