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參數(shù)資料
| 型號(hào)： | AD80066KRSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CTLR 16BIT 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 類型： | 信號(hào)處理器 |
| 輸入類型： | 模擬 |
| 輸出類型： | 數(shù)字 |
| 接口： | 串行 |
| 電流 - 電源： | 95mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
AD80066
Rev. A | Page 15 of 20
INTERNAL REGISTER DETAILS
CONFIGURATION REGISTER
The configuration register controls the AD80066 operating mode
and bias levels. The D8, D7, and D6 bits should always be set low.
Bit D2 sets the full-scale input voltage range of the AD80066 ADC
to either 3 V (high) or 1.5 V (low). Bit D5 controls the internal
voltage reference. If the AD80066 internal voltage reference is
used, this bit is set low. Setting Bit D5 high disables the internal
voltage reference, allowing an external voltage reference to be
used. Setting Bit D3 low enables the CDS mode of operation and
setting this bit high enables the SHA mode of operation. If Bit D4
is set high, the 16-bit ADC output is multiplexed into two bytes.
The most significant byte is output on the ADCCLK rising edge,
and the least significant byte is output on the ADCCLK falling
edge (see Figure 10). If Bit D1 is set high, the AD80066 is con-
figured for slow operation (8 MHz) to reduce power consumption.
Bit D0 controls the power-down mode. Setting Bit D0 low places the
AD80066 into a very low power sleep mode. All register contents
are retained while the AD80066 is in the power-down state.
MUX REGISTER
The mux register controls the sampling channel order in the
AD80066. The D8, D7, D6, and D5 bits should always be set
low. Bit D4 is used when operating in 4-channel mode. Setting
Bit D4 low sequences the multiplexer to sample the A channel
first, and then the B, C, and D channels. When in this mode,
the CDSCLK2 pulse always resets the multiplexer to sample the
A channel first. When Bit D4 is set high, the channel order is
reversed to D, C, B, and A. The CDSCLK2 pulse always resets the
multiplexer to sample the D channel first. Bits D[3:0] are used
when operating in 1-channel mode. Bit D3 is set high to sample
the A channel. Bit D2 is set high to sample the B channel. Bit D1
is set high to sample the C channel. Bit D0 is set high to sample the
D channel. The multiplexer remains stationary in 1-channel mode.
PGA GAIN REGISTERS
There are four PGA registers for individually programming the
gain for the A, B, C, and D channels. The D8, D7, and D6 bits in
each register must be set low, and the D5 through D0 bits control
the gain range in 64 increments. See Figure 22 for the PGA gain vs.
the PGA register value. The coding for the PGA registers is straight
binary, with a word of all 0s corresponding to the minimum gain
setting (1×) and a word of all 1s corresponding to the maximum
gain setting (5.9×).
OFFSET REGISTERS
There are four offset registers for individually programming the
offset in the A, B, C, and D channels. The D8 through D0 bits
control the offset range from 300 mV to +300 mV in 512 incre-
ments. The coding for the offset registers is sign magnitude, with
D8 as the sign bit. Table 11 shows the offset range as a function
of the D8 through D0 bits.
Table 8. Configuration Register Settings
D8
D7
D6
D5
D4
D3
D2
D1
D0
Set to 0
Internal voltage
reference
2/1 byte output
CDS operation
Input range
Fast/slow
Power mode
1 = disabled
1 = one byte
1 = SHA mode
1 = 3 V
1 = 8 MHz
1 = on (normal)
0 = enabled1
0 = two bytes1
0 = CDS mode1
0 = 1.5 V1
0 = 24 MHz1
0 = off1
1 Power-on default.
Table 9. Mux Register Settings
D8
D7
D6
D5
D4
D3
D2
D1
D0
Set to 0
Mux order
Channel A
Channel B
Channel C
Channel D
1 = D, C, B, A
1 = channel used
0 = A, B, C, D
0 = not used1
1 Power-on default.
Table 10. PGA Gain Register Settings
(MSB)
(LSB)
D81
D71
D61
D5
D4
D3
D2
D1
D0
Gain (V/V)
Gain (dB)
0
02
1.0
0.0
0
1
1.013
0.12
…
0
1
0
5.56
14.9
0
1
5.9
15.56
1 Must be set to 0.
2 Power-on default.
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