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參數(shù)資料
| 型號： | AD80066KRSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/21頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CTLR 16BIT 28SSOP |
| 標(biāo)準包裝： | 47 |
| 類型： | 信號處理器 |
| 輸入類型： | 模擬 |
| 輸出類型： | 數(shù)字 |
| 接口： | 串行 |
| 電流 - 電源： | 95mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
AD80066
Rev. A | Page 18 of 20
ANALOG INPUTS—SHA MODE
Figure 19 shows the analog input configuration for the SHA
mode of operation. Figure 20 shows the internal timing for the
sampling switches. The input signal is sampled when CDSCLK2
transitions from high to low, opening S1. The voltage on the
OFFSET pin is also sampled on the falling edge of CDSCLK2,
when S2 opens. S3 is then closed, generating a differential
output voltage that represents the difference between the
sampled input voltage and the OFFSET voltage. The input
clamp is disabled during SHA mode operation.
AD80066
S1
2pF
S3
CML
INPUT SIGNAL
S2
2pF
CML
OFFSET
OPTIONAL DC OFFSET
(OR CONNECT TO GND)
VINA
VINB
VINC
VIND
A
B
C
D
CML
08
55
2-
01
9
Figure 19. SHA Mode Input Configuration (All Four Channels Are Identical)
CDSCLK2
Q3
(INTERNAL)
S1, S2 CLOSED
S3 CLOSED
S3 OPEN
S1, S2 OPEN
08
55
2-
02
0
Figure 20. SHA Mode Internal Switch Timing
Figure 21 shows how the OFFSET pin can be used in a CIS
application for coarse offset adjustment. Many CIS signals have
dc offsets ranging from several hundred millivolts to more than
1 V. By connecting the appropriate dc voltage to the OFFSET pin,
the large dc offset is removed from the CIS signal. Then, the
signal can be scaled using the PGA to maximize the dynamic
range of the ADC.
AD80066
OFFSET
A OFFSET
VINA
VINB
VINC
0.1F
AVDD
VOLTAGE
REFERENCE
FROM CIS
MODULE
R1
B OFFSET
C OFFSET
DC OFFSET
R2
SHA
08
55
2-
02
1
Figure 21. SHA Mode Used with External DC Offset
PROGRAMMABLE GAIN AMPLIFIERS (PGA)
The AD80066 uses one PGA for each channel. Each PGA has a
gain range from 1× (0 dB) to 5.8× (15.5 dB), adjustable in
64 steps. Figure 22 shows the PGA gain as a function of the
PGA register value. Although the gain curve is approximately
linear-in-dB, the gain in V/V varies nonlinearly with register
code, following the equation
+
=
63
4.9
1
5.9
G
Gain
where G is the decimal value of the gain register contents and
varies from 0 to 63.
GA
IN
(
V
/V
)
5.9
PGA REGISTER VALUE (Decimal)
0
GA
IN
(
d
B
)
1
5
12
9
6
3
0
5.0
4.0
3.0
2.0
1.0
4
8 12 16 20 24 28 32 36 40 44 48 52 56 60 63
08
55
2-
0
22
Figure 22. PGA Gain Transfer Function
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| AD80066KRSZRL | 功能描述:IC DSP CTLR 16BIT 28SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
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