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參數(shù)資料
| 型號： | AD8004 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad Current Feedback Amplifier(電流反饋四路放大器) |
| 中文描述： | 四電流反饋放大器（電流反饋四路放大器） |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 291K |
| 代理商： | AD8004 |
AD8004
REV. A
–12–
T able I. Recommended Component Values and T ypical Bandwidths
Alternate
–2
Alternate
–1
Alternate
+1
Alternate
+2
Gain
AD8004AN (DIP)
PAC K AGE T Y PE
R
F
(
)
R
G
(
)
R
T
(
)
Small Signal BW
@
±
5 V
S
(MHz)
Peaking @
±
5 V
S
0.1 dB Flatness
@
±
5 V
S
(MHz)
Small Signal BW
@ +5 V
S
(MHz)
AD8004AR (SOIC )
PAC K AGE T Y PE
R
F
(
)
R
G
(
)
R
T
(
)
Small Signal BW
@
±
5 V
S
(MHz)
Peaking @
±
5 V
S
0.1 dB Flatness
@
±
5 V
S
(MHz)
Small Signal BW
@ +5 V
S
(MHz)
–10
–2
–1
+1
+2
+10
499
49.9
None
698
348
57.6
499
249
61.9
649
649
53.6
499
499
54.9
1.21 k
–
50
806
–
50
1.10 k
1.10 k
50
698
698
50
499
54.9
50
155
< 0.3 dB
125
None
180
0.3 dB
135
None
190
0.3 dB
150
1.3 dB
250
1.7 dB
115
< 0.14 dB
185
0.4 dB
135
< 0.3 dB
–
25
–
30
–
–
–
35
–
–
135
105
155
120
160
130
200
95
150
120
499
49.9
None
698
348
57.6
499
249
61.9
750
750
53.6
499
499
54.9
1.10 k
–
50
698
–
50
1.10 k
1.10 k
50
604
604
50
499
54.9
50
155
< 0.7 dB
130
< 0.1 dB
190
0.5 dB
125
None
195
0.4 dB
150
1.3 dB
225
1.8 dB
110
< 0.1 dB
175
0.5 dB
135
< 0.2 dB
–
35
–
25
–
–
–
30
–
–
135
115
175
110
165
130
195
95
155
120
NOT ES
1
R
chosen for 50
characteristic input impedance.
2
Resistor values listed are standard 1% tolerance.
T he PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance ground path. T he ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Fig-
ure 39). One end should be connected to the ground plane
and the other within 1/8 in. of each power pin. An additional
(4.7
μ
F–10
μ
F) tantalum electrolytic capacitor should be con-
nected in parallel.
T he feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance greater than 1 pF at the inverting input
will significantly affect high speed performance when operating
at low noninverting gains. An example of extra inverting input
capacitance can be seen on Figure 36 plot.
Stripline design techniques should be used for long signal traces
(greater than about 1 in.). T hese should be designed with the
proper system characteristic impedance and be properly termi-
nated at each end.
C1
0.1μF
C2
0.1μF
C4
10μF
C3
10μF
R
T
INVERTING CONFIGURATION
V
IN
V
OUT
+V
S
–V
S
R
G
R
F
R
bT
, 50
C1
0.1μF
C2
0.1μF
C4
10μF
C3
10μF
R
T
NONINVERTING CONFIGURATION
V
IN
V
OUT
+V
S
–V
S
R
G
R
F
1/4
1/4
R
bT
, 50
Figure 39. Inverting and Noninverting Configurations
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