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參數(shù)資料
| 型號： | AD8002 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual 600 MHz, 50 mW Current Feedback Amplifier(600MHz,50mW雙電流反饋放大器) |
| 中文描述： | 雙600兆赫，50毫瓦電流反饋放大器（頻率600MHz，50mW的雙電流反饋放大器） |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 507K |
| 代理商： | AD8002 |
9
REV. B
AD8002
–13–
Single-E nded to Differential Driver Using an AD8002
T he two halves of an AD8002 can be configured to create a
single-ended to differential high speed driver with a –3dB band-
width in excess of 200 MHz as shown in Figure 47. Although
the individual op amps are each current feedback, the overall
architecture yields a circuit with attributes normally associated
with voltage feedback amplifiers, while offering the speed advan-
tages inherent in current feedback amplifiers. In addition, the
gain of the circuit can be changed by varying a single resistor,
R
F
, which is often not possible in a dual op amp differential
driver.
50
OUTPUT #1
50
OUTPUT #2
R
G
511
R
F
511
C
C
0.5–1.5pF
1/2
AD8002
1/2
AD8002
OP AMP #1
OP AMP #2
V
IN
R
A
511
R
A
511
511
R
B
511
R
B
Figure 47. Differential Line Driver
T he current feedback nature of the op amps, in addition to
enabling the wide bandwidth, provides an output drive of more
than 3 V p-p into a 20
load for each output at 20 MHz. On
the other hand, the voltage feedback nature provides symmetri-
cal high impedance inputs and allows the use of reactive compo-
nents in the feedback network.
T he circuit consists of the two op amps each configured as a
unity gain follower by the 511
R
A
feedback resistors between
each op amp’s output and inverting input. T he output of each
op amp has a 511
R
B
resistor to the inverting input of the
other op amp. T hus, each output drives the other op amp
through a unity gain inverter configuration. By connecting the
two amplifiers as cross-coupled inverters, their outputs are freed
to be equal and opposite, assuring zero-output common-mode
voltage.
With this circuit configuration, the common-mode signal of the
outputs is reduced. If one output moves slightly higher, the
negative input to the other op amp drives its output to go
slightly lower and thus preserves the symmetry of the comple-
mentary outputs which reduces the common-mode signal. T he
common-mode output signal was measured to be –50 dB at
1 MHz.
Looking at this configuration overall, there are two high imped-
ance inputs (the + inputs of each op amp), two low impedance
outputs and high open loop gain. If we consider the two
noninverting inputs and just the output of Op Amp #2, the
structure looks like a voltage feedback op amp having two sym-
metrical, high impedance inputs and one output. T he +input to
Op Amp #2 is the noninverting input (it has the same polarity
as Output #2) and the +input to Amplifier #1 is the inverting
input (opposite polarity of Output #2).
With a feedback resistor R
F
, an input resistor R
G
, and grounding
of the +input of Op Amp #2, a feedback amplifier is formed.
T his configuration is just like a voltage feedback amplifier in an
inverting configuration if only Output #2 is considered. T he ad-
dition of Output #1 makes the amplifier differential output.
T he differential gain of this circuit is:
G
=
R
F
R
G
×
1
+
R
A
R
B
T he R
F
/R
G
term is the gain of the overall op amp configuration
and is the same as for an inverting op amp except for the polar-
ity. If Output #1 is used as the output reference, then the gain is
positive. T he 1+R
A
/R
B
term is the noise gain of each individual
op amp in its noninverting configuration.
T he resulting architecture offers several advantages. First, the
gain can be changed by changing a single resistor. Changing
either R
F
or R
G
will change the gain as in an inverting op amp
circuit. For most types of differential circuits, more than one
resistor must be changed to change gain and still maintain good
CMR.
Reactive elements can be used in the feedback network. T his is
in contrast to current feedback amplifiers that restrict the use of
reactive elements in the feedback. T he circuit described requires
about 0.9 pF of capacitance in shunt across R
F
in order to opti-
mize peaking and realize a –3 dB bandwidth of more than
200 MHz.
T he peaking exhibited by the circuit is very sensitive to the value
of this capacitor. Parasitics in the board layout on the order of
tenths of picofarads will influence the frequency response and
the value required for the feedback capacitor, so a good layout is
essential.
T he shunt capacitor type selection is also critical. A good micro-
wave type chip capacitor with high Q was found to yield best
performance. T he part selected for this circuit was a muRata
Erie part no. MA280R9B.
T he distortion was measured at 20 MHz with a 3 V p-p input
and a 100
load on each output. For Output #1 the distortion
is –37 dBc and –41 dBc for the second and third harmonics
respectively. For Output #2 the second harmonic is –35dBc
and the third harmonic is –43 dBc.
+6
–4
–14
1M
10M
1G
100M
–6
–8
–10
–12
–2
0
+2
+4
O
FREQUENCY – Hz
OUT+
OUT–
C
C
= 0.9pF
Figure 48. Differential Driver Frequency Response
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