參數(shù)資料
型號(hào)： AD7999YRJZ-1RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 8BIT 4CH I2C SOT23-8
產(chǎn)品變化通告： AD7991,5,9 Offset Error Change 17/Sept/2010
設(shè)計(jì)資源： Using AD8599 as an Ultralow Distortion Driver for the AD7999 (CN0045)
標(biāo)準(zhǔn)包裝： 10,000
位數(shù)： 8
采樣率（每秒）： 1M
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 4.68mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-8
供應(yīng)商設(shè)備封裝： SOT-23-8
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)單端，單極
AD7991/AD7995/AD7999
Rev. B | Page 17 of 28
THEORY OF OPERATION
The AD7991/AD7995/AD7999 are low power, 12-/10-/8-bit,
single-supply, 4-channel ADCs. Each part can be operated from
a single 2.35 V to 5.5 V supply.
The AD7991/AD7995/AD7999 provide the user with a 4-channel
multiplexer, an on-chip track-and-hold, an ADC, and an I2C-
compatible serial interface, all housed in an 8-lead SOT-23 package
that offers the user considerable space-saving advantages over
alternative solutions.
The AD7991/AD7995/AD7999 normally remains in a power-
down state while not converting. Therefore, when supplies are
first applied, the part is in a power-down state. Power-up is initiated
prior to a conversion, and the device returns to the power-down
state upon completion of the conversion. This automatic power-
down feature allows the device to save power between conversions.
This means any read or write operations across the I2C interface
can occur while the device is in power-down.
CONVERTER OPERATION
The AD7991/AD7995/AD7999 are successive approximation
ADCs built around a capacitive DAC. Figure 18 and Figure 19
show simplified schematics of the ADC during its acquisition
and conversion phases, respectively. Figure 18 shows the ADC
during its acquisition phase: SW2 is closed, SW1 is in Position A,
the comparator is held in a balanced condition, and the sampling
capacitor acquires the signal on VIN. The source driving the
analog input needs to settle the analog input signal to within
one LSB in 0.6 μs, which is equivalent to the duration of the
power-up and acquisition time.
06
46
1-
0
20
CAPACITIVE
DAC
VIN
COMPARATOR
CONTROL
LOGIC
SW1
A
B
SW2
AGND
Figure 18. ADC Acquisition Phase
When the ADC starts a conversion, as shown in Figure 19, SW2
opens and SW1 moves to Position B, causing the comparator to
become unbalanced. The input is disconnected when the con-
version begins. The control logic and the capacitive DAC are used
to add and subtract fixed amounts of charge from the sampling
capacitor to bring the comparator back into a balanced condition.
When the comparator is rebalanced, the conversion is complete.
The control logic generates the ADC output code. Figure 20 shows
the ADC transfer function.
06
46
1-
02
1
VIN
COMPARATOR
CONTROL
LOGIC
SW1
A
B
SW2
AGND
CAPACITIVE
DAC
Figure 19. ADC Conversion Phase
ADC Transfer Function
The output coding of the AD7991/AD7995/AD7999 is straight
binary. The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size for
the AD7991/AD7995/AD7999 is VREF/4096, VREF/1024, and
VREF/256, respectively. Figure 20 shows the ideal transfer
characteristics for the AD7991/AD7995/AD7999.
111 ... 111
111 ... 110
111 ... 000
A
D
C
CO
DE
AGND + 1 LSB
ANALOG INPUT
0V TO REFIN
AD7991 1 LSB = REFIN/4096
AD7995 1 LSB = REFIN/1024
AD7999 1 LSB = REFIN/256
+REFIN – 1 LSB
011 ... 111
000 ... 010
000 ... 001
000 ... 000
06
46
1-
02
2
Figure 20. AD7991/AD7995/AD7999 Transfer Characteristics
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