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參數(shù)資料
| 型號： | AD7999YRJZ-1RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 4CH I2C SOT23-8 |
| 產(chǎn)品變化通告： | AD7991,5,9 Offset Error Change 17/Sept/2010 |
| 設計資源： | Using AD8599 as an Ultralow Distortion Driver for the AD7999 (CN0045) |
| 標準包裝： | 10,000 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 4.68mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應商設備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極 |
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AD7991/AD7995/AD7999
Rev. B | Page 21 of 28
SAMPLE DELAY AND BIT TRIAL DELAY
It is recommended that no I2C bus activity occur while a
conversion is taking place (see Figure 27 and the Placing the
However, if this is not always possible, then in order to maintain
the performance of the ADC, Bits D0 and D1 in the configuration
register are used to delay critical sample intervals and bit trials
from occurring while there is activity on the I2C bus. This results in
a quiet period for each bit decision. However, the sample delay
protection may introduce excessive jitter, degrading the SNR for
large signals above 300 Hz. For guaranteed ac performance, use
of clock stretching is recommended.
When Bit D0 and Bit D1 are both 0, the bit trial and sample interval
delay mechanism is implemented. The default setting of D0 and D1
is 0. To turn off both delay mechanisms, set D0 and D1 to 1.
CONVERSION RESULT REGISTER
The conversion result register is a 16-bit read-only register that
stores the conversion result from the ADC in straight binary
format. A 2-byte read is necessary to read data from this
register. Table 12 shows the contents of the first byte to be read
from AD7991/AD7995/AD7999, and Table 13 shows the
contents of the second byte to be read.
Each AD7991/AD7995/AD7999 conversion result consists of
two leading 0s, two channel identifier bits, and the 12-/10-/8-bit
data result. For the AD7995, the two LSBs (D1 and D0) of the
second read contain two trailing 0s. For the AD7999, the four
LSBs (D3, D2, D1, and D0) of the second read contain four
trailing 0s.
Table 12. Conversion Value Register (First Read)
D15
D14
D13
D12
D11
D10
D9
D8
Leading 0
CHID1
CHID0
MSB
B10
B9
B8
Table 13. Conversion Value Register (Second Read)
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3/0
B2/0
B1/0
B0/0
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