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參數(shù)資料
| 型號(hào)： | AD7994BRUZ-0 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 4CHAN I2C 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 188k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.2mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極 |
| 產(chǎn)品目錄頁面： | 780 (CN2011-ZH PDF) |
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AD7993/AD7994
Rev. 0 | Page 22 of 32
CYCLE TIMER REGISTER
The cycle timer register is an 8-bit read/write register that stores
the conversion interval value for the automatic cycle interval
mode of the AD7993/AD7994 (see the Modes of Operation
section). D5 to D3 of the cycle timer register are unused and
should contain 0s at all times. On power-up, the cycle timer
register contains all 0s, thus disabling automatic cycle operation
of the AD7993/AD7994. To enable automatic cycle mode, the
user must write to the cycle timer register, selecting the required
conversion interval. Table 24 shows the structure of the cycle
timer register while Table 25 shows how the bits in this register
are decoded to provide various automatic sampling intervals.
Table 24. Cycle Timer Register and Default Power-Up Settings
D7
D6
D5
D4
D3
D2
D1
D0
Sample
Delay
Bit Trial
Delay
0
Cyc
Bit2
Cyc
Bit1
Cyc
Bit0
0
Table 25. Cycle Timer Intervals
D2
D1
D0
Typical Conversion Interval
(TCONVERT = conversion time of the ADC)
0
Mode not selected
0
1
TCONVERT × 32
0
1
0
TCONVERT × 64
0
1
TCONVERT × 128
1
0
TCONVERT × 256
1
0
1
TCONVERT × 512
1
0
TCONVERT × 1024
1
TCONVERT × 2048
SAMPLE DELAY AND BIT TRIAL DELAY
It is recommended that no I2C bus activity occur when a
conversion is taking place. However, if this is not possible, for
example when operating in Mode 2 or Mode 3, then in order to
maintain the performance of the ADC, Bits D7 and D6 in the
cycle timer register are used to delay critical sample intervals
and bit trials from occurring while there is activity on the I2C
bus. This results in a quiet period for each bit decision. In
certain cases where there is excessive activity on the interface
lines, this may have the effect of increasing the overall
conversion time. However, if bit trial delays extend longer than
1 s, the conversion terminates.
When Bits D7 and D6 are both 0, the bit trial and sample
interval delaying mechanism is implemented. The default
setting of D7 and D6 is 0. To turn off both delay mechanisms,
set D7 and D6 to 1.
Table 26. Cycle Timer Register and Defaults at Power-Up
D7
D6
D5
D4
D3
D2
D1
D0
Sample
Delay
Bit Trial
Delay
0
Cyc
Bit 2
Cyc
Bit 1
Cyc
Bit 0
0
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| AD7994BRUZ-0REEL | 功能描述:IC ADC 12BIT 4CHAN I2C 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個(gè)單端，雙極；8 個(gè)差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| AD7994BRUZ-1 | 功能描述:IC ADC 12BIT 4CHAN I2C 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| AD7994BRUZ-1REEL | 功能描述:IC ADC 12BIT 4CHAN I2C 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| AD7994-X | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 10- and 12-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP |
| AD7995 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 12-/10-/8-Bit ADC with I2C-Compatible Interface in 8-Lead SOT-23 |
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