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參數(shù)資料

型號(hào)：	AD7994BRUZ-0
廠商：	Analog Devices Inc
文件頁(yè)數(shù)：	14/32頁(yè)
文件大?。?/td>	0K
描述：	IC ADC 12BIT 4CHAN I2C 16TSSOP
標(biāo)準(zhǔn)包裝：	96
位數(shù)：	12
采樣率（每秒）：	188k
數(shù)據(jù)接口：	I²C，串行
轉(zhuǎn)換器數(shù)目：	1
功率耗散（最大）：	2.2mW
電壓電源：	單電源
工作溫度：	-40°C ~ 125°C
安裝類型：	表面貼裝
封裝/外殼：	16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝：	16-TSSOP
包裝：	管件
輸入數(shù)目和類型：	4 個(gè)單端，單極
產(chǎn)品目錄頁(yè)面：	780 (CN2011-ZH PDF)

AD7993/AD7994

Rev. 0 | Page 21 of 32

Hysteresis Register (CH1/CH2/CH3/CH4)

Each hysteresis register is a 16-bit read/write register, of which

only the 12 LSBs of the register are used. The hysteresis register

stores the hysteresis value, N, when using the limit registers.

Each pair of limit registers has a dedicated hysteresis register.

The hysteresis value determines the reset point for the ALERT

pin/Alert_Flag if a violation of the limits has occurred. For

example, if a hysteresis value of 8 LSB is required on the upper

and lower limits of Channel 1, the 12-bit word, 0000 0000 0000

1000, should be written to the hysteresis register of CH1, the

address of which is shown in Table 8. On power-up, the

hysteresis registers contain a value of 8 LSB for the AD7994 and

2 LSB for the AD7993. If a different hysteresis value is required,

that value must be written to the hysteresis register for the

channel in question. For the AD7993, D1 and D0 of the

hysteresis register should contain 0s.

Table 20. Hysteresis Register (First Read/Write)

D15

D14

D13

D12

D11

D10

B11

B10

Table 21. Hysteresis Register (Second Read/Write)

Using the Limit Registers to Store Min/Max Conversion

Results for CH1 to CH4

If full scale, that is, all 1s, is written to the hysteresis register for

a particular channel, the DATAHIGH and DATALOW registers for

that channel no longer act as limit registers as previously

described, but instead act as storage registers for the maximum

and minimum conversion results returned from conversions on

a channel over any given period of time. This function is useful

in applications where the widest span of actual conversion

results is required rather than using the alert to signal that an

intervention is necessary. This function could be useful for

monitoring temperature extremes during refrigerated goods

transportation.

It must be noted that on power-up, the contents of the

DATAHIGH register for each channel are full scale, while the

contents of the DATALOW registers are zero scale by default.

Therefore, minimum and maximum conversion values being

stored in this way are lost if power is removed or cycled.

ALERT STATUS REGISTER

The alert status register is an 8-bit read/write register that

provides information on an alert event. If a conversion results in

activating the ALERT pin or the Alert_Flag bit in the

conversion result register, as described in the Limit Registers

section, the alert status register may be read to gain further

information. It contains two status bits per channel, one

corresponding to the DATAHIGH limit and the other to the

DATALOW limit. The bit with a status of 1 shows where the

violation occurred—that is, on which channel—and whether

the violation occurred on the upper or lower limit. If a second

alert event occurs on the other channel between receiving the

first alert and interrogating the alert status register, the

corresponding bit for that alert event is also set.

The entire contents of the alert status register may be cleared by

writing 1, 1 to Bits D2 and D1 in the configuration register, as

shown in Table 12. This may also be achieved by writing all 1s

to the alert status register itself. Therefore, if the alert status

contents of the alert status register are cleared or reset to all 0s.

Table 22. Alert Status Register

CH4HI

CH4LO

CH3HI

CH3LO

CH2HI

CH2LO

CH1HI

CH1LO

Table 23. Alert Status Register Bit Function Descriptions

Bit

Mnemonic

Comment

CH1LO

Violation of DATALOW limit on Channel 1 if

this bit set to 1, no violation if bit is set to 0.

CH1HI

Violation of DATAHIGH limit on Channel 1 if