參數(shù)資料
型號(hào): AD7984BRMZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 8/24頁
文件大?。?/td> 0K
描述: IC ADC 18BIT 1.3MSPS SAR 10MSOP
設(shè)計(jì)資源: Converting a Single-Ended Signal with AD7984 Differential PulSAR ADC (CN0033)
標(biāo)準(zhǔn)包裝: 1,000
系列: PulSAR®
位數(shù): 18
采樣率(每秒): 1.33M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 14mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分,單極
AD7984
Rev. A | Page 16 of 24
DIGITAL INTERFACE
Although the AD7984 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7984 is compatible with SPI, QSPI,
digital hosts, and DSPs. In this mode, the AD7984 can use
either a 3-wire or 4-wire interface. A 3-wire interface using the
CNV, SCK, and SDO signals minimizes wiring connections
useful, for instance, in isolated applications. A 4-wire interface
using the SDI, CNV, SCK, and SDO signals allows CNV, which
initiates the conversions, to be independent of the readback
timing (SDI). This is useful in low jitter sampling or
simultaneous sampling applications.
When in chain mode, the AD7984 provides a daisy-chain feature
using the SDI input for cascading multiple ADCs on a single
data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected,
the chain mode is always selected.
In either mode, the AD7984 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must timeout
the maximum conversion time prior to readback.
The busy indicator feature is enabled
In CS mode if CNV or SDI is low when the ADC
conversion ends (see
and
).
In chain mode if SCK is high during the CNV rising edge
(see Figure 39).
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