參數(shù)資料
型號(hào): AD7984BRMZ-RL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 11/24頁(yè)
文件大?。?/td> 0K
描述: IC ADC 18BIT 1.3MSPS SAR 10MSOP
設(shè)計(jì)資源: Converting a Single-Ended Signal with AD7984 Differential PulSAR ADC (CN0033)
標(biāo)準(zhǔn)包裝: 1,000
系列: PulSAR®
位數(shù): 18
采樣率(每秒): 1.33M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 14mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分,單極
AD7984
Rev. A | Page 19 of 24
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7984s are connected
to an SPI-compatible digital host.
A connection diagram example using two AD7984s is shown in
Figure 32, and the corresponding timing is given in Figure 33.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7984
enters the acquisition phase and goes into standby mode. Each
ADC result can be read by bringing its SDI input low, which
consequently outputs the MSB onto SDO. The remaining data
bits are then clocked by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can be
used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided it has an acceptable
hold time. After the 18th SCK falling edge or when SDI goes
high (whichever occurs first), SDO returns to high impedance
and another AD7984 can be read.
AD7984
SDI
SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
CS1
CS2
AD7984
SDI
SDO
CNV
SCK
069
73
-02
2
Figure 32. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
SDO
D17
D16
D15
D1
D0
tDIS
SCK
12
3
34
35
36
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI(CS1)
CNV
tSSDICNV
tHSDICNV
D1
16
17
tSCK
tSCKL
tSCKH
D0
D17
D16
19
20
18
SDI(CS2)
0
69
73
-0
23
Figure 33. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
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