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參數(shù)資料
| 型號(hào)： | AD7980BRMZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | ADC 16BIT 1MSPS LP 10-MSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 9mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)偽差分，單極 |
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AD7980
Data Sheet
Rev. C | Page 18 of 28
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7980 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 33, and the
corresponding timing is given in Figure 34.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7980 then enters the acquisition phase and
powers down. The data bits are clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
If multiple AD7980s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
06392-
017
AD7980 SDO
SDI
DATA IN
IRQ
DIGITAL HOST
CONVERT
CLK
VIO
47kΩ
CNV
SCK
Figure 33. 3-Wire CS Mode with Busy Indicator
Connection Diagram (SDI High)
06392-
018
tCONV
tCNVH
tCYC
AQUISITION
tACQ
tSCK
tSCKH
tSCKL
CONVERSION
SCK
CNV
SDI = 1
SDO
D15
D14
D1
D0
tHSDO
1
2
3
15
16
17
tDSDO
tDIS
Figure 34. 3-Wire CS Mode with Busy Indicator Serial Interface Timing (SDI High)
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