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參數(shù)資料
| 型號(hào)： | AD7980ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 15/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 1MSPS SAR 10LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 10mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 10-LFCSP-WD（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)偽差分，單極 |
| 其它名稱(chēng)： | AD7980ACPZ-RL7DKR |
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AD7980
Data Sheet
Rev. C | Page 22 of 28
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7980s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7980s is shown
in Figure 41, and the corresponding timing is given in Figure 42.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7980 ADC labeled C in Figure 41) is
driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7980 then enters the acquisition phase and powers
down. The data bits stored in the internal shift register are
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N + 1 clocks are required to
readback the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows a
faster reading rate and, consequently, more AD7980s in the chain,
provided the digital host has an acceptable hold time.
06392-
025
AD7980
C
SDO
SDI
DATA IN
IRQ
DIGITAL HOST
CONVERT
CLK
CNV
SCK
AD7980
B
SDO
SDI
CNV
SCK
AD7980
A
SDO
SDI
CNV
SCK
Figure 41. Chain Mode with Busy Indicator Connection Diagram
06392-
026
tCONV
tCYC
tSSDISCK
tSCKH
tSCK
tHSDISC
tACQ
tDSDOSDI
tDSDODSI
AQUISITION
tSSDICNV
AQUISITION
tSCKL
CONVERSION
tHSDICNV
SCK
CNV = SDIA
SDOA = SDIB
SDOB = SDIC
SDOC
tEN
DA15
DA14
DA13
DB15
DB14
DB13
DC15
DC14
DC13
DB1
DB0
DA15
DA14
DA1
DA0
DC1
DC0
DB15
DB14
DA0
DA1
DB0
DB1
DA14
DA15
DA1
DA0
tHSDO
1
2
3
15
16
17
4
18
19
31
32
33
34
35
47
48
49
tDSDO
tDSDOSDI
Figure 42. Chain Mode with Busy Indicator Serial Interface Timing
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