參數(shù)資料
型號(hào)： AD7980ACPZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/28頁(yè)
文件大小： 0K
描述： IC ADC 16BIT 1MSPS SAR 10LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 10mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 10-LFCSP-WD（3x3）
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 1 個(gè)偽差分，單極
其它名稱： AD7980ACPZ-RL7DKR
Data Sheet
AD7980
Rev. C | Page 19 of 28
CS MODE 4-WIRE, WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7980s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7980s is shown in
Figure 35, and the corresponding timing is given in Figure 36.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum conversion
time to avoid the generation of the busy signal indicator.
When the conversion is complete, the AD7980 enters the
acquisition phase and powers down. Each ADC result can be
read by bringing its SDI input low, which consequently outputs
the MSB onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the 16th SCK
falling edge or when SDI goes high, whichever is earlier, SDO
returns to high impedance and another AD7980 can be read.
06392-
019
DIGITAL HOST
CONVERT
CS2
CS1
CLK
DATA IN
AD7980 SDO
SDI
CNV
SCK
AD7980 SDO
SDI
CNV
SCK
Figure 35. 4-Wire CS Mode Without Busy Indicator Connection Diagram
06392-
020
tCONV
tCYC
AQUISITION
tACQ
tSCK
tSCKH
tSCKL
CONVERSION
SCK
CNV
tSSDICNV
tHSDICNV
SDO
D15
D13
D14
D1
D0
D15
D14
D1
D0
tHSDO
tEN
1
2
3
14
15
16
17
18
30
31
32
tDSDO
tDIS
SDI(CS1)
SDI(CS2)
Figure 36. 4-Wire CS Mode Without Busy Indicator Serial Interface Timing
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