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參數(shù)資料
| 型號： | AD7942BCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 250KSPS 10-LFCSP |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤，CSP |
| 供應商設備封裝： | 10-LFCSP-WD（3x3） |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
| 配用： | EVAL-AD7942CB-ND - BOARD EVALUATION FOR AD7942 |
| 其它名稱： | AD7942BCPZRL7DKR |
AD7942
Rev. B | Page 22 of 2
4
Chain Mode with Busy Indicator
This mode can also be used to daisy-chain multiple AD7942s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applica-
tions or for systems with a limited interfacing capacity. Data
readback is analogous to clocking a shift register. A connection
diagram example using three AD7942s is shown in Figure 40
and the corresponding timing diagram is given in Figure 41.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, SDO in the near end ADC
(ADC C in Figure 40) is driven high. This transition on SDO
can be used as a busy indicator to trigger the data readback
controlled by the digital host. The AD7942 then enters the
acquisition phase and powers down. The data bits stored in the
internal shift register are then clocked out, MSB first, by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first, and
14 × N + 1 clocks are required to readback the N ADCs.
Although the rising edge can be used to capture the data, a
digital host also using the SCK falling edge allows a faster
reading rate and consequently more AD7942s in the chain,
provided the digital host has an acceptable hold time. For
instance, with a 5 ns digital host setup time and a 3 V interface,
up to eight AD7942s running at a conversion rate of 220 kSPS
can be daisy-chained to a single 3-wire port.
CNV
SCK
SDO
SDI
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
AD7942
C
CNV
SCK
SDO
SDI AD7942
B
04
65
7-
0
40
CNV
SCK
SDO
SDI AD7942
A
Figure 40. Chain Mode with Busy Indicator Connection Diagram
04
65
7-
04
1
SDOA = SDIB
DA13 DA12 DA11
SCK
12
3
35
41
42
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV = SDIA
DA1
413
tSCK
tSCKH
tSCKL
DA0
15
31
14
SDOB = SDIC
DB13 DB12 DB11
DA1
DB1DB0DA13 DA12
43
tSSDISCK
tHSDISCK
tHSDO
tDSDO
SDOC
DC13 DC12 DC11
DA1DA0
DC1DC0DA12
17
27
28
16
29
DB1DB0DA13
DB13 DB12
tDSDOSDI
tSSCKCNV
tHSCKCNV
DA0
tDSDOSDI
Figure 41. Chain Mode with Busy Indicator, Serial Interface Timing
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