參數(shù)資料
型號(hào): AD7940BRMZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 1/20頁(yè)
文件大?。?/td> 0K
描述: IC ADC 14BIT UNIPOLAR 8-MSOP
標(biāo)準(zhǔn)包裝: 50
位數(shù): 14
采樣率(每秒): 100k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 26.4mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)單端,單極
3 mW, 100 kSPS,
14-Bit ADC in 6-Lead SOT-23
Rev. A
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rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
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Tel: 781.329.4700
Fax: 781.461.3113
2004–2011 Analog Devices, Inc. All rights reserved.
FEATURES
Fast throughput rate: 100 kSPS
Specified for VDD of 2.5 V to 5.5 V
Low power
4 mW typ at 100 kSPS with 3 V supplies
17 mW typ at 100 kSPS with 5 V supplies
Wide input bandwidth:
81 dB SINAD at 10 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI/QSPI/MICROWIRE/DSP compatible
Standby mode: 0.5 A max
6-Lead SOT-23 and 8-Lead MSOP packages
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Remote data acquisition systems
FUNCTIONAL BLOCK DIAGRAM
03305-0-001
VIN
VDD
GND
AD7940
SCLK
SDATA
CS
T/H
14-BIT SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
Figure 1.
Table 1. 16-Bit and 14-Bit ADC (MSOP and SOT-23)
Type
100 kSPS
250 kSPS
500 kSPS
16-Bit True Differential
16-Bit Pseudo Differential
16-Bit Unipolar
14-Bit True Differential
14-Bit Pseudo Differential
14-Bit Unipolar
GENERAL DESCRIPTION
The AD79401 is a 14-bit, fast, low power, successive
approximation ADC. The part operates from a single 2.50 V to
5.5 V power supply and features throughput rates up to 100 kSPS.
The part contains a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 7 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is also initiated at this
point. There are no pipelined delays associated with the part.
The AD7940 uses advanced design techniques to achieve very
low power dissipation at fast throughput rates. The reference for
the part is taken internally from VDD, which allows the widest
dynamic input range to the ADC. Thus, the analog input range
for this part is 0 V to VDD. The conversion rate is determined by
the SCLK frequency.
1Protected by US. Patent No. 6,681,332.
This part features a standard successive approximation ADC
with accurate control of the sampling instant via a CS input and
once off conversion control.
PRODUCT HIGHLIGHTS
1. First 14-bit ADC in a SOT-23 package.
2. High throughput with low power consumption.
3. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced when a power-down mode is used while not
converting. The part also features a shutdown mode to
maximize power efficiency at lower throughput rates.
Power consumption is 0.5 A max when in shutdown.
4. Reference derived from the power supply.
5. No pipeline delay.
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