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| 型號： | AD7939BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/36頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 8CH PARALL 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 1.5M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 13.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；4 個(gè)差分，單極；4 個(gè)偽差分，單極；7 偽差分，單極 |
| 配用： | EVAL-AD7939CBZ-ND - BOARD EVALUATION FOR AD7939CBZ |
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Data Sheet
AD7938/AD7939
Rev. C | Page 23 of 36
Using the Sequencer: Programmable Sequence
(SEQ = 0, SHDW = 1)
The AD7938/AD7939 can be configured to automatically cycle
through a number of selected channels using the on-chip
programmable sequencer by setting SEQ = 0 and SHDW = 1 in
the control register. The analog input channels to be converted
are selected by setting the relevant bits in the shadow register
to 1 (see Table 12).
Once the shadow register has been programmed with the
required sequence, the next conversion executed is on the
lowest channel programmed in the SHDW register. The next
conversion executed is on the next highest channel in the
sequence and so on. When the last channel in the sequence
is converted, the internal multiplexer returns to the first
channel selected in the shadow register and commences the
sequence again.
It is not necessary to write to the control register again once a
sequencer operation has been initiated. The WR input must be
kept high to ensure that the control register is not accidentally
overwritten or that a sequence operation is not interrupted. If
the control register is written to at any time during the sequence,
ensure that the SEQ and SHDW bits are set to 1, 0 to avoid
interrupting the conversion sequence. The sequence program
remains in force until such time as the AD7938/AD7939 is
written to and the SEQ and SHDW bits are configured with any
bit combination except 1, 0. Figure 32 shows a flow chart of the
programmable sequence operation.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION
SET SEQ = 0 SHDW = 1.
INITIATE A WRITE CYCLE.
THIS WRITE CYCLE IS TO PROGRAM THE SHADOW REGISTER.
SET RELEVANT BITS TO SELECT
THE CHANNELS TO BE INCLUDED IN THE SEQUENCE.
SEQ BIT = 1
SHDW BIT = 0
CONTINUOUSLY CONVERT
CONSECUTIVE
CHANNELS SELECTED
WITH EACH CONVST PULSE
BUT ALLOWS THE RANGE,
CODING, ANALOG INPUT TYPE,
ETC BITS IN THE CONTROL
REGISTER TO BE CHANGED
WITHOUT INTERRUPTING
THE SEQUENCE.
CONTINUOUSLY CONVERT
CONSECUTIVE
CHANNELS SELECTED
IN THE SHADOW REGISTER
WITH EACH CONVST PULSE.
04
75
1-
0
39
WR = HIGH
SEQ BIT = 0
SHDW BIT = 1
Figure 32. Programmable Sequence Flow Chart
Consecutive Sequence (SEQ = 1, SHDW = 1)
A sequence of consecutive channels can be converted beginning
with Channel 0 and ending with a final channel selected by
writing to the ADD2 to ADD0 bits in the control register. This
is done by setting the SEQ and SHDW bits in the control
register to 1. In this mode, the sequencer can be used without
having to write to the shadow register. To set this mode up, the
next conversion, once the control register is written to, is on
Channel 0, then Channel 1, and so on, until the channel
selected by the address bits (ADD2 to ADD0) is reached. The
cycle begins again provided the WR input is tied high. If low,
the SEQ and SHDW bits must be set to 1, 0 to allow the ADC to
continue its preprogrammed sequence uninterrupted. Figure 33
shows the flowchart of the consecutive sequence mode.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION SELECT
FINAL CHANNEL (ADD2 TO ADD0) IN
CONSECUTIVE SEQUENCE.
SET SEQ = 1 SHDW = 1.
CONTINUOUSLY CONVERT A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0
UP TO AND INCLUDING THE PREVIOUSLY
SELECTED FINAL CHANNEL ON ADD2 TO ADD0
WITH EACH CONVST PULSE.
SEQ BIT = 1
SHDW BIT = 0
CONTINUOUSLY CONVERT
CONSECUTIVE CHANNELS SELECTED
WITH EACH CONVST PULSE BUT
ALLOWS THE RANGE, CODING, ANALOG
INPUT TYPE, ETC. BITS IN THE
CONTROL REGISTER TO BE CHANGED
WITHOUT INTERRUPTING
THE SEQUENCE.
03
71
5-
04
0
Figure 33. Consecutive Sequence Mode Flow Chart
REFERENCE
The AD7938/AD7939 can operate with either the on-chip
reference or external reference. The internal reference is
selected by setting the REF bit in the internal control register
to 1. A block diagram of the internal reference circuitry is
shown in Figure 34. The internal reference circuitry includes an
on-chip 2.5 V band gap reference and a reference buffer. When
using the internal reference, the VREFIN/VREFOUT pin should be
decoupled to AGND with a 0.47 μF capacitor. This internal
reference not only provides the reference for the analog-to-
digital conversion, but it can also be used externally in the
system. It is recommended that the reference output is buffered
using an external precision op amp before applying it anywhere
in the system.
REFERENCE
AD7938/
AD7939
ADC
BUFFER
03
71
5-
04
1
VREFIN/
VREFOUT
Figure 34. Internal Reference Circuit Block Diagram
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