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| 型號： | AD7939BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 8CH PARALL 32LFCSP |
| 標準包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 1.5M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 13.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 8 個單端，單極；4 個差分，單極；4 個偽差分，單極；7 偽差分，單極 |
| 配用： | EVAL-AD7939CBZ-ND - BOARD EVALUATION FOR AD7939CBZ |
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AD7938/AD7939
Data Sheet
Rev. C | Page 22 of 36
220
10k
2 × VREF p-p
GND
440
220
220
20k
220
27
27
V+
V–
V+
V–
A
VIN+
VIN–
VREF
AD7938/
AD7939
0.47F
03715-
035
3.75V
2.5V
1.25V
3.75V
2.5V
1.25V
+
Figure 28. Dual Op Amp Circuit to Convert a Single-Ended
Bipolar Signal into a Differential Unipolar Signal
10k
VREF p-p
VREF
GND
440
220
220
20k
220
27
27
V+
V–
V+
V–
A
VIN+
VIN–
VREF
AD7938/
AD7939
0.47F
03715-
036
3.75V
2.5V
1.25V
3.75V
2.5V
1.25V
+
Figure 29. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal
into a Differential Signal
Another method of driving the AD7938/AD7939 is to use the
single-ended-to-differential amplifier or as a differential-to-
differential amplifier. The device is as easy to use as an op amp
and greatly simplifies differential signal amplification and
driving.
Pseudo Differential Mode
The AD7938/AD7939 can have four pseudo differential pairs
(Pseudo Mode 1) or seven pseudo differential inputs (Pseudo
Mode 2) by setting the MODE0 and MODE1 bits in the control
register to 1, 0 and 1, 1, respectively. In the case of the four
pseudo differential pairs, VIN+ is connected to the signal source,
which must have an amplitude of VREF (or 2 × VREF depending
on the range chosen) to make use of the full dynamic range of
the part. A dc input is applied to the VIN pin. The voltage
applied to this input provides an offset from ground or a pseudo
ground for the VIN+ input. In the case of the seven pseudo
differential inputs, the seven analog input signals inputs are
referred to a dc voltage applied to VIN7.
The benefit of pseudo differential inputs is that they separate
the analog input signal ground from the ADC ground, allowing
dc common-mode voltages to be cancelled. Typically, this range
can extend from 0.3 V to +0.7 V when VDD = 3 V or 0.3 V to
for pseudo differential mode.
VIN+
VIN–
VREF
AD7938/
AD7939*
*ADDITIONAL PINS OMITTED FOR CLARITY.
03715-
037
VREF p-p
0.47F
DC INPUT
VOLTAGE
+
Figure 30. Pseudo Differential Mode Connection Diagram
ANALOG INPUT SELECTION
As shown in Table 10, users can set up their analog input
configuration by setting the values in the MODE0 and MODE1
bits in the control register. Assuming the configuration has been
chosen, there are different ways of selecting the analog input to
be converted depending on the state of the SEQ and SHDW bits
in the control register.
Traditional Multichannel Operation (SEQ = SHDW = 0)
Any one of eight analog input channels or four pairs of channels
can be selected for conversion in any order by setting the SEQ
and SHDW bits in the control register to 0. The channel to be
converted is selected by writing to the address bits, ADD2 to
ADD0, in the control register to program the multiplexer prior
to the conversion. This mode of operation is that of a traditional
multichannel ADC where each data write selects the next
channel for conversion. Figure 31 shows a flowchart of this
mode of operation. The channel configurations are shown in
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION.
SET SEQ = SHDW = 0. SELECT THE DESIRED
CHANNEL TO CONVERT (ADD2 TO ADD0).
ISSUE CONVST PULSE TO INITIATE A CONVERSION
ON THE SELECTED CHANNEL.
INITIATE A READ CYCLE TO READ THE DATA
FROM THE SELECTED CHANNEL.
INITIATE A WRITE CYCLE TO SELECT THE NEXT
CHANNEL TO BE CONVERTED BY
CHANGING THE VALUES OF BITS ADD2 TO ADD0
IN THE CONTROL REGISTER. SEQ = SHDW = 0.
03715-
038
Figure 31. Traditional Multichannel Operation Flow Chart
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