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參數(shù)資料
| 型號： | AD7938BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | MO-220-VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 20/32頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | AD7938BCP |
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AD7938/AD7939
Preliminary Technical Data
0.47
μ
F
+1.25V
V
IN
R
R
3R
0V
–1.25V
+2.5V
0V
V
IN0
V
IN7
V
REFOUT
AD7938/
AD7939*
*ADDITIONAL PINS OMITTED FOR CLARITY
0
Figure 24. THD vs. Analog Input Frequency for Various Source Impedances
Figure 25
frequency for various supplies while sampling at 1.5 MHz with
an SCLK of 20 MHz. In this case, the source impedance is 10 .
Figure 25. THD vs. Analog Input Frequency for Various Supply Voltages
shows a graph of the THD versus the analog input
ANALOG INPUTS
The AD7938/AD7939 have software selectable analog input
configurations. The user can choose either eight single-ended
inputs, four fully differential pairs, four pseudo-differential
pairs, or seven pseudo-differential inputs. The analog input
configuration is chosen by setting the MODE0/MODE1 bits in
the internal control register (see
Single-Ended Mode
The AD7938/AD7939 can have eight single-ended analog input
channels by setting the MODE0 and MODE1 bits in the control
register to 0. In applications where the signal source has a high
impedance, it is recommended to buffer the analog input before
applying it to the ADC. The analog input range can be
programmed to be either 0 to V
REF
or 0 to 2 × V
REF
.
).
Table 9
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it of the correct format for the ADC.
Figure 26
the ADC in single-ended mode.
Figure 26. Single-Ended Mode Connection Diagram
Differential Mode
The AD7938/AD7939 can have four differential analog input
pairs by setting the MODE0 and MODE1 bits in the control
register to 0 and 1, respectively.
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. F
defines the fully differential analog
input of the AD7938/AD7939.
igure 27
Figure 27. Differential Input Definition
0
V
REF
p-p
V
IN+
V
IN–
REF
V
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7938/
AD7939*
COMMON-MODE
VOLTAGE
The amplitude of the differential signal is the difference
between the signals applied to the V
IN+
and V
IN
pins in each
differential pair (i.e., V
IN+
V
IN
). V
IN+
and V
IN
should be
simultaneously driven by two signals each of amplitude V
REF
that are 180° out of phase (assuming the 0 to V
REF
range is
selected). The amplitude of the differential signal is therefore
V
REF
to +V
REF
peak-to-peak (i.e., 2 × V
REF
). This is regardless of
the common mode (CM). The common mode is the average of
the two signals, i.e. (V
IN+
+ V
IN
)/2 and is therefore the voltage
that the two inputs are centered on. This results in the span of
each input being CM ± V
REF
/2. This voltage has to be set up
externally and its range varies with V
REF
. As the value of V
REF
increases, the common-mode range decreases. When driving
the inputs with an amplifier, the actual common-mode range is
determined by the amplifier’s output voltage swing.
Figure 28 and
typically varies with V
REF
for a 5 V power supply using the 0 to
V
REF
range or 2 × V
REF
range, respectively. The common mode
must be in this range to guarantee the functionality of the
AD7938/AD7939.
show how the common-mode range
Figure 29
shows a typical connection diagram when operating
Rev. PrN | Page 20 of 32
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