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| 型號： | AD7934BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 4CH 1.5MSPS 28TSSOP |
| 標準包裝： | 50 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.5M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 13.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極；2 個偽差分，單極 |
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AD7933/AD7934
Rev. B | Page 28 of 32
AD7933/AD7934 to ADSP-21065L Interface
Figure 42 shows a typical interface between the AD7933/AD7934
and the ADSP-21065L SHARC processor. This interface is an
example of one of three DMA handshake modes. The MSX
control line is actually three memory select lines. Internal
ADDR25 to 24 are decoded into MS3 to 0, these lines are then
asserted as chip selects. The DMAR1 (DMA Request 1) is used
in this setup as the interrupt to signal the end of the conversion.
The rest of the interface is standard handshaking operation.
AD7933/
AD7934*
ADSP-21065L*
WR
DB0 TO DB11
D0 TO D31
ADDR0 TO ADDR23
MSX
DMAR1
BUSY
CS
CONVST
DSP/USER SYSTEM
WR
RD
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
03
71
3-
0
45
Figure 42. Interfacing to the ADSP-21065L
AD7933/AD7934 to TMS32020, TMS320C25, and
TMS320C5x Interface
Parallel interfaces between the AD7933/AD7934 and the
TMS32020, TMS320C25 and TMS320C5x family of DSPs are
shown in Figure 43. Select the memory-mapped address for the
AD7933/AD7934 to fall in the I/O memory space of the DSPs.
The parallel interface on the AD7933/AD7934 is fast enough to
interface to the TMS32020 with no extra wait states. If high
speed glue logic, such as 74AS devices, is used to drive the
RD and the WR lines when interfacing to the TMS320C25, no
wait states are necessary. However, if slower logic is used, data
accesses may be slowed sufficiently when reading from, and
writing to, the part to require the insertion of one wait state.
Extra wait states are necessary when using the TMS320C5x at
their fastest clock speeds (see the TMS320C5x User’s Guide
for details).
Data is read from the ADC using the following instruction:
IN D, ADC
where:
D is the data memory address.
ADC is the AD7933/AD7934 address.
AD7933/
AD7934*
TMS32020/
TMS320C25/
TMS320C50*
WR
RD
DB11 TO DB0
DMD0 TO DMD15
A0 TO A15
IS
READY
INTX
BUSY
CS
EN
CONVST
DSP/USER SYSTEM
TMS320C25
ONLY
R/W
STRB
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
DATA BUS
ADDRESS
DECODER
03
71
3-
0
46
MSC
Figure 43. Interfacing to TMS32020/TMS320C25/TMS320C5x
AD7933/AD7934 to 80C186 Interface
Figure 44 shows the AD7933/AD7934 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent, high speed DMA channels where data transfers
can occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7933/AD7934 finish a conversion,
the BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation, which also resets the interrupt latch. Sufficient
priority must be assigned to the DMA channel to ensure that
the DMA request is serviced before the completion of the next
conversion.
AD7933/
AD7934*
80C186*
WR
DB0 TO DB11
AD0 TO AD15
A16 TO A19
ALE
DRQ1
BUSY
CS
QR
S
CONVST
MICROPROCESSOR/
USER SYSTEM
WR
RD
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS/DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
03
71
3-04
7
Figure 44. Interfacing to the 80C186
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