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| 型號： | AD7934BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 4CH 1.5MSPS 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.5M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 13.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極；2 個偽差分，單極 |
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AD7933/AD7934
Rev. B | Page 21 of 32
220
10k
2×VREF p-p
GND
440
220
20k
220
27
V+
V–
V+
V–
A
VIN+
VIN–
VREF
AD7933/
AD7934
0.47F
03
71
3-
0
35
3.75V
2.5V
1.25V
3.75V
2.5V
1.25V
+
Figure 27. Dual Op Amp Circuit to Convert a Single-Ended
Bipolar Signal into a Unipolar Differential Signal
10k
VREF p-p
VREF
GND
440
220
27
V+
V–
V+
V–
A
VIN+
VIN–
VREF
AD7933/
AD7934
0.47F
03
71
3-
03
6
3.75V
2.5V
1.25V
3.75V
2.5V
1.25V
Figure 28. Dual Op Amp Circuit to Convert a Single-Ended Unipolar
Signal into a Differential Signal
Another method of driving the AD7933/AD7934 is to use the
AD8138 differential amplifier. The AD8138 can be used as a
single-ended-to-differential amplifier, or differential-to-differential
amplifier. The device is as easy to use as an op amp and greatly
simplifies differential signal amplification and driving.
Pseudo Differential Mode
The AD7933/AD7934 can have two pseudo differential pairs by
setting the MODE0 and MODE1 bits in the control register to 1
and 0, respectively. VIN+ is connected to the signal source and
must have an amplitude of VREF (or 2 × VREF depending on the
range chosen) to make use of the full dynamic range of the part.
A dc input is applied to the VIN pin. The voltage applied to this
input provides an offset from ground or a pseudo ground for
the VIN+ input. The benefit of pseudo differential inputs is that
they separate the analog input signal ground from the ADC
ground, allowing the cancellation of dc common-mode
voltages. Typically, this range can extend to 0.3 V to +0.7 V
shows a connection diagram for pseudo differential mode.
VIN+
VIN–
VREF
AD7933/
AD7934*
*ADDITIONAL PINS OMITTED FOR CLARITY.
VREF p-p
0.47F
DC INPUT
VOLTAGE
03
71
3-
03
7
+
Figure 29. Pseudo Differential Mode Connection Diagram
ANALOG INPUT SELECTION
As shown in Table 10, users can set up their analog input
configuration by setting the values in the MODE0 and MODE1
bits in the control register. Assuming the configuration has been
chosen, there are two different ways of selecting the analog
input to be converted depending on the state of the SEQ0 and
SEQ1 bits in the control register.
Traditional Multichannel Operation (SEQ0 = SEQ1 = 0)
Any one of four analog input channels or two pairs of channels
can be selected for conversion in any order by setting the SEQ0
and SEQ1 bits in the control register to 0. The channel to be
converted is selected by writing to the address bits, ADD1 and
ADD0, in the control register to program the multiplexer prior
to the conversion. This mode of operation is that of a traditional
multichannel ADC where each data write selects the next
channel for conversion. Figure 30 shows a flowchart of this
mode of operation. The channel configurations are shown in
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION
SET SEQ0 = SEQ1 = 0. SELECT THE DESIRED
CHANNEL TO CONVERT ON (ADD1 TO ADD0).
ISSUE CONVST PULSE TO INITIATE A CONVERSION
ON THE SELECTED CHANNEL.
INITIATE A READ CYCLE TO READ THE DATA
FROM THE SELECTED CHANNEL.
INITIATE A WRITE CYCLE TO SELECT THE NEXT
CHANNEL TO BE CONVERTED ON BY
CHANGING THE VALUES OF BITS ADD2 TO ADD0
IN THE CONTROL REGISTER. SEQ0 = SEQ1 = 0.
0
37
13
-0
38
Figure 30. Traditional Multichannel Operation Flow Chart
Using the Sequencer: Consecutive Sequence
(SEQ0 = 1, SEQ1 = 1)
A sequence of consecutive channels can be converted beginning
with Channel 0 and ending with a final channel selected by
writing to the ADD1 and ADD0 bits in the control register. This
is done by setting the SEQ0 and SEQ1 bits in the control
register both to 1. Once the control register is written to, the
next conversion is on Channel 0, then Channel 1, and so on
until the channel selected by the Address Bit ADD1 and Address
Bit ADD0 is reached. The ADC then returns to Channel 0 and
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