
Data Sheet
AD7927
Rev. D | Page 15 of 28
WRITE BIT = 0
03
08
8-
0
13
CS
DUMMY CONVERSION
DIN = ALL 1s
WRITE BIT = 1,
SEQ = 1,
SHADOW = 0
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A2 TO CHANNEL A0
FOR CONVERSION.
SEQ = 1, SHADOW = 1
DOUT: CONVERSION RESULT FROM CHANNEL 0
CONTINUOUSLY CONVERTS ON A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0 UP
TO AND INCLUDING THE PREVIOUSLY SELECTED
A2 TO CHANNEL A0 IN THE CONTROL REGISTER
CONTINUOUSLY CONVERTS ON THE SELECTED
SEQUENCE OF CHANNELS BUT ALLOWS
RANGE, CODING AND SO ON, TO CHANGE IN THE
CONTROL REGISTER WITHOUT INTERRUPTING
THE SEQUENCE, PROVIDED SEQ = 1, SHADOW = 0
POWER-ON
Figure 13. SEQ and SHADOW Conversion Flowchart to Convert a Sequence of
Consecutive Channels
CIRCUIT INFORMATION
The AD7927 is a high speed, 8-channel, 12-bit, single-supply
ADC. The part can be operated from a 2.7 V to 5.25 V supply.
When operated from either a 5 V or 3 V supply, the AD7927 is
capable of throughput rates of 200 kSPS. The conversion time
may be as short as 800 ns when provided with a 20 MHz clock.
The AD7927 provides the user with an on-chip, track-and-hold
ADC and a serial interface housed in a 20-lead TSSOP. The
AD7927 has eight single-ended input channels with a channel
sequencer, allowing the user to select a channel sequence
through which the ADC can cycle with each consecutive CS
falling edge. The serial clock input accesses data from the part,
controls the transfer of data written to the ADC, and provides
the clock source for the successive approximation ADC. The
analog input range for the AD7927 is 0 V to REFIN or 0 V to
2 × REFIN, depending on the status of Bit 1 in the control register.
For the 0 to 2 × REFIN range, the part must be operated from a
4.75 V to 5.25 V supply.
The AD7927 provides flexible power management options
to allow the user to achieve the best power performance for a
given throughput rate. These options are selected by program-
ming the power management bits, PM1 and PM0, in the control
register.
CONVERTER OPERATION
The AD7927 is a 12-bit successive approximation ADC based
around a capacitive DAC. The AD7927 can convert analog input
signals in the range 0 V to REFIN or 0 V to 2 × REFIN. Figure 14 is comprised of control logic, SAR, and a capacitive DAC that
are used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a bal-
phase. SW2 is closed and SW1 is in Position A. The comparator
is held in a balanced condition and the sampling capacitor
acquires the signal on the selected VIN channel.
A
B
SW1
SW2
COMPARATOR
4k
CAPACITIVE
DAC
CONTROL
LOGIC
AGND
VIN0
VIN7
03
08
8-
01
4
Figure 14. ADC Acquisition Phase
opens and SW1 moves to Position B, causing the comparator
to become unbalanced. The control logic and the capacitive
DAC are used to add and subtract fixed amounts of charge
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
functions.
A
B
SW1
SW2
COMPARATOR
4k
CAPACITIVE
DAC
CONTROL
LOGIC
AGND
VIN0
VIN7
03
08
8-
01
5
Figure 15. ADC Conversion Phase
ANALOG INPUT
Figure 16 shows an equivalent circuit of the analog input struc-
ture of the AD7927. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 300 mV. This causes these diodes to become forward
biased and start conducting current into the substrate. 10 mA is
the maximum current these diodes can conduct without caus-
ing irreversible damage to the part. Capacitor C1, in
Figure 16is typically about 4 pF and can primarily be attributed to pin
capacitance. The Resistor R1 is a lumped component made up
of the on resistance of a switch (track-and-hold switch) and also
includes the on resistance of the input multiplexer. The total
resistance is typically about 400 Ω. The capacitor, C2, is the
ADC sampling capacitor and has a capacitance of 30 pF typically.