參數(shù)資料
型號(hào)： AD7927BRU
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 8CH 200KSPS 20TSSOP
標(biāo)準(zhǔn)包裝： 75
位數(shù)： 12
采樣率（每秒）： 200k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 7.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極
配用： EVAL-AD7927CBZ-ND - BOARD EVALUATION FOR AD7927
AD7927
Data Sheet
Rev. D | Page 20 of 28
AUTO SHUTDOWN (PM1 = 0, PM0 = 1)
In this mode, the AD7927 automatically enters shutdown at the
end of each conversion when the control register is updated.
When the part is in shutdown, the track-and-hold is in hold
mode. Figure 23 shows the general diagram of the operation
of the AD7927 in this mode. In shutdown mode all internal
circuitry on the AD7927 is powered down. The part retains
information in the control register during shutdown. The AD7927
remains in shutdown until the next CS falling edge it receives.
On this CS falling edge, the track-and-hold that was in hold
while the part was in shutdown returns to track. Wake-up time
from auto shutdown is 1 μs maximum, and the user should
ensure that 1 μs has elapsed before attempting a valid conversion.
When running the AD7927 with a 20 MHz clock, one dummy
16 SCLK transfer should be sufficient to ensure the part is fully
powered up. During this dummy transfer, the contents of the
control register should remain unchanged; therefore, the
WRITE bit should be 0 on the DIN line.
Depending on the SCLK frequency used, this dummy transfer
may affect the achievable throughput rate of the part, with every
other data transfer being a valid conversion result. If, for example,
the maximum SCLK frequency of 20 MHz was used, the auto
shutdown mode could be used at the full throughput rate of
200 kSPS without affecting the throughput rate at all. Only a
portion of the cycle time is taken up by the conversion time and
the dummy transfer for wake-up.
In this mode, the power consumption of the part is greatly
reduced with the part entering shutdown at the end of each
conversion. When the control register is programmed to move
into auto shutdown, it does so at the end of the conversion. The
user can move the ADC in and out of the low power state by
controlling the CS signal.
1
SCLK
DOUT
DIN
16
1
16
DUMMY CONVERSION
CHANNEL IDENTIFIER BITS + CONVERSION RESU LT
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESU LT
12
03
08
8-
0
23
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS, PM1 = 0, PM0 = 1
CONTROL REGISTER SHOULD NOT
CHANGE, WRITE BIT = 0
TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 1
IN CONTROL REGISTER OR SET WRITE BIT = 0
DATA INTO CONTROL/SHADOW REGISTER
DATA IN TO CONTROL/SHADOW REGISTER
16
CS
PART ENTERS SHUTDOWN ON CS
RISING EDGE AS PM1 = 0, PM0 = 1
PART BEGINS TO POWER UP
ON CS FALLING EDGE
PART IS FULLY
POWERED UP
PART ENTERS SHUTDOWN ON
CS RISING EDGE AS PM1 = 0, PM0 = 1
Figure 23. Auto Shutdown Mode Operation
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