All input signals are specified with tr = " />
參數(shù)資料
型號： AD7911AUJZ-R2
廠商： Analog Devices Inc
文件頁數(shù)： 26/28頁
文件大小： 0K
描述： IC ADC 10BIT 250KSPS TSOT23-8
標準包裝： 1
位數(shù)： 10
采樣率（每秒）： 250k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉換器數(shù)目： 1
功率耗散（最大）： 20mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-8 薄型，TSOT-23-8
供應商設備封裝： TSOT-23-8
包裝： 標準包裝
輸入數(shù)目和類型： 2 個單端，單極
其它名稱： AD7911AUJZ-R2DKR
AD7911/AD7921
Rev. A | Page 7 of 28
TIMING SPECIFICATIONS
Guaranteed by characterization.
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
10
kHz min2
5
MHz max
tCONVERT
16 × tSCLK
AD7921
14 × tSCLK
AD7911
tQUIET
30
ns min
Minimum quiet time required between bus relinquish and start of next conversion
t1
15
ns min
Minimum CS pulse width
t2
10
ns min
CS to SCLK setup time
30
ns max
Delay from CS until DOUT three-state is disabled
45
ns max
DOUT access time after SCLK falling edge
t5
0.4 tSCLK
ns min
SCLK low pulse width
t6
0.4 tSCLK
ns min
SCLK high pulse width
10
ns min
SCLK to DOUT valid hold time
t8
5
ns min
DIN setup time prior to SCLK falling edge
t9
6
ns min
DIN hold time after SCLK falling edge
30
ns max
SCLK falling edge to DOUT three-state
10
ns min
SCLK falling edge to DOUT three-state
tPOWER-UP6
1
μs max
Power-up time from full power-down
1 Mark/space ratio for SCLK input is 40/60 to 60/40.
2 Minimum fSCLK at which specifications are guaranteed.
3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross VIH or VIL voltage.
4 Measured with a 50 pF load capacitor.
5 T10 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
TIMING DIAGRAMS
04350-0-002
200
μAI
OL
200
μAI
OH
1.6V
TO OUTPUT
PIN
CL
50pF
Figure 2. Load Circuit for Digital Output Timing Specifications
04350-0-003
SCLK
VIH
VIL
DOUT
t4
Figure 3. Access Time after SCLK Falling Edge
04350-0-004
SCLK
VIH
VIL
DOUT
t7
Figure 4. Hold Time after SCLK Falling Edge
04350-0-005
SCLK
1.6V
DOUT
t10
Figure 5. SCLK Falling Edge to DOUT Three-State
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相關代理商/技術參數(shù)
參數(shù)描述
AD7911AUJZ-REEL7 功能描述:IC ADC 10BIT 250KSPS TSOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應商設備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個單端，雙極；8 個差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494
AD7912 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel, 2.35 V to 5.25 V, 1 MSPS, 10-/12-Bit ADCs
AD7912ARM 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 10-bit Serial 8-Pin MSOP 制造商:Rochester Electronics LLC 功能描述:DUAL 10-BIT, 1MSPS, ADC I.C - Bulk 制造商:Analog Devices 功能描述:10BIT ADC DUAL SMD 7912 MSOP8
AD7912ARM-REEL 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 10-bit Serial 8-Pin MSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 10-BIT SERL 8MSOP - Tape and Reel
AD7912ARM-REEL7 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 10-bit Serial 8-Pin MSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 10-BIT SERL 8MSOP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:DUAL 10-BIT, 1MSPS, ADC I.C - Tape and Reel
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