參數(shù)資料
型號(hào)： AD7890ARZ-10REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/28頁(yè)
文件大?。?/td> 0K
描述： IC DAS 12BIT 8CH 24-SOIC
產(chǎn)品培訓(xùn)模塊： Power Line Monitoring
標(biāo)準(zhǔn)包裝： 1,000
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
分辨率（位）： 12 b
采樣率（每秒）： 117k
數(shù)據(jù)接口： 串行
電壓電源： 單電源
電源電壓： 5V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 帶卷 (TR)
AD7890
Rev. C | Page 13 of 28
conversion, the part returns to its tracking mode. The acquisition
time of the track/ hold amplifier begins at this point.
REFERENCE
The AD7890 contains a single reference pin, labeled REF OUT/
REF IN, which either provides access to the part’s own 2.5 V
reference or to which an external 2.5 V reference can be connected
to provide the reference source for the part. The part is specified
with a 2.5 V reference voltage. Errors in the reference source results
in gain errors in the AD7890’s transfer function and adds to the
specified full-scale errors on the part. On the AD7893-10, it also
results in an offset error injected in the attenuator stage.
The AD7890 contains an on-chip 2.5 V reference. To use this
reference as the reference source for the AD7890, simply connect a
0.1 μF disc ceramic capacitor from the REF OUT/REF IN pin to
AGND. The voltage which appears at this pin is internally buffered
before being applied to the ADC. If this reference is required for
use external to the AD7890, it should be buffered as the source
impedance of this output is 2 kΩ nominal. The tolerance on the
internal reference is ±10 mV at 25°C with a typical temperature
coefficient of 25 ppm/°C and a maximum error over temperature
of ±25 mV.
If the application requires a reference with a tighter tolerance or
the AD7890 needs to be used with a system reference, then the
user has the option of connecting an external reference to this
REF OUT/REF IN pin. The external reference effectively
overdrives the internal reference and thus provides the reference
source for the ADC. The reference input is buffered, but has a
nominal 2 kΩ resistor connected to the AD7890’s internal
reference. Suitable reference sources for the AD7890 include the
AD680, AD780, and REF-43 precision 2.5 V references.
TIMING AND CONTROL
The AD7890 is capable of two interface modes, selected by the
SMODE input. The first of these is a self-clocking mode where
the part provides the frame sync, serial clock, and serial data at
the end of conversion. In this mode the serial clock rate is
determined by the master clock rate of the part (at the CLK IN
input). The second mode is an external clocking mode where
the user provides the frame sync and serial clock signals to obtain
the serial data from the part. In this second mode, the user has
control of the serial clock rate up to a maximum of 10 MHz. The
two modes are discussed in the Serial Interface section.
The part also provides hardware and software conversion start
features. The former provides a well-defined sampling instant
with the track/hold going into hold on the rising edge of the
CONVST signal. For the software conversion start, a write to
the CONV bit to the control register initiates the conversion
sequence. However, for the software conversion start an internal
pulse has to time out before the input signal is sampled. This
pulse, plus the difficulty in maintaining exactly equal delays
between each software conversion start command, means that
the dynamic performance of the AD7890 may have difficulty
meeting specifications when used in software conversion start
mode. The AD7890 provides separate channel select and
conversion start control. This allows the user to optimize the
throughput rate of the system. Once the track/hold has gone into
hold mode, the input channel can be updated and the input voltage
can settle to the new value while the present conversion is in
progress.
Assuming the internal pulse has timed out before the CONVST
pulse is exercised, the conversion consists of 14.5 master clock
cycles. In the self-clocking mode, the conversion time is defined
as the time from the rising edge of CONVST to the falling edge
of RFS (for example, when the device starts to transmit its
conversion result). This time includes the 14.5 master clock
cycles plus the updating of the output register and delay time in
outputting the RFS signal, resulting in a total conversion time of
5.9 μs maximum. Figure 6 shows the conversion timing for the
AD7890 when used in the self-clocking (master) mode with
hardware CONVST. The timing diagram assumes that the
internal pulse is not active when the CONVST signal goes high.
To ensure this, the channel address to be converted should be
selected by writing to the control register prior to the CONVST
pulse. Sufficient setup time should be allowed between the
control register write and the CONVST to ensure that the internal
pulse has timed out. The duration of the internal pulse (and hence
the duration of setup time) depends on the value of CEXT.
TRACK/HOLD GOES
INTO THE HOLD
THREE-STATE
NOTES:
1. (I) SIGNIFIES AN INPUT.
2. (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.
DATA OUT (O)1
SCLK (O)
RFS (O)
CONVST (I)
tCONVERT
0
1357-
006
Figure 6. Self-Clocking (Master) Mode Conversion Sequence
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