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| 型號： | AD7879ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT CTLR TOUCH 16LFCSP |
| 標(biāo)準包裝： | 1 |
| 類型： | 電阻 |
| 觸摸面板接口： | 4 線 |
| 輸入數(shù)/鍵： | 1 TSC |
| 分辨率（位）： | 12 b |
| 評估套件： | 可供 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 數(shù)據(jù)速率/采樣率 (SPS，BPS)： | 105k |
| 電壓基準： | 內(nèi)部 |
| 電源電壓： | 1.6 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-VQ |
| 包裝： | 標(biāo)準包裝 |
| 其它名稱： | AD7879ACPZ-RLDKR |
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AD7879/AD7889
Rev. C | Page 35 of 40
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH.
3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [01011XX], WHERE THE Xs ARE DON'T CARE BITS.
4. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
SDA
DEV
A6
DEV
A5
DEV
A4
R/W
SCL
DEV
A3
1
2
3
4
17
DEV
A2
DEV
A1
DEV
A0
ACK
A7
A6
11
16
5
6
7
8
9
10
START
AD7879-1/AD7889-1 DEVICE ADDRESS
A1
A0
REGISTER ADDRESS[A7:A0]
D15
D14
D9
D8
26
18
19
20
25
28
27
34
29
35
D1
D0
D7
D6
REGISTER DATA[D15:D8]
REGISTER DATA[D7:D0]
ACK
36
37
ACK
STOP
DEV
A6
DEV
A5
DEV
A4
1
2
3
START
t
1
AD7879-1/AD7889-1
DEVICE ADDRESS
07667-
042
t
3
t
2
t
4
t
5
t
6
t
8
t
7
Figure 43. Example of I2C Timing for Single Register Write Operation
Writing Data over the I2C Bus
The process of writing to the AD7879-1/AD7889-1 over the I2C
bus is shown in Figure 43 and Figure 45. The device address is
sent over the bus followed by the R/W bit set to 0. This is followed
by one byte of data that contains the 8-bit address of the internal
data register to be written. The bit map in Table 26 shows the
register address byte.
Table 26. I2C Register Address Byte
MSB
LSB
7
6
5
4
3
2
1
0
Register Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The third data byte contains the eight MSBs of the data to be
written to the internal register. The fourth data byte contains
the eight LSBs of data to be written to the internal register.
The AD7879-1/AD7889-1 address pointer register automatically
increments after each write. This allows the master to sequentially
write to all registers on the AD7879-1/AD7889-1 in the same
write transaction. However, the address pointer register does
not wrap after the last address.
Any data written to the AD7879-1/AD7889-1 after the address
pointer has reached its maximum value is discarded.
All registers on the AD7879-1/AD7889-1 have 16 bits. Two
consecutive 8-bit data bytes are combined and written to the
16-bit registers. To avoid errors, all writes to the device must
contain an even number of data bytes.
To end the transaction, the master generates a stop condition on
SDA, or it generates a repeat start condition if the master is to
maintain control of the bus.
Reading Data over the I2C Bus
To read from the AD7879-1/AD7889-1, the address pointer
register must first be set to the address of the required internal
register. The master performs a write transaction and writes to
the AD7879-1/AD7889-1 to set the address pointer. The master
then outputs a repeat start condition to keep control of the bus
or, if this is not possible, the master ends the write transaction
with a stop condition. A read transaction is initiated, with the
R/W bit set to 1.
The AD7879-1/AD7889-1 supply the upper eight bits of data
from the addressed register in the first readback byte, followed
by the lower eight bits in the next byte. This is shown in Figure 44
and Figure 45.
Because the address pointer automatically increments after each
read, the AD7879-1/AD7889-1 continue to output readback data
until the master puts a no acknowledge and a stop condition on
the bus. If the address pointer reaches its maximum value and
the master continues to read from the part, the AD7879-1/
AD7889-1 repeatedly send data from the last register addressed.
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