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參數資料
| 型號： | AD7877ACBZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 18/45頁 |
| 文件大小： | 0K |
| 描述： | IC CTRLR TOUCH SCREEN 25-WLCSP |
| 標準包裝： | 1 |
| 類型： | 電阻 |
| 觸摸面板接口： | 4 線 |
| 輸入數/鍵： | 1 TSC |
| 分辨率（位）： | 12 b |
| 評估套件： | 可供 |
| 數據接口： | 串行，SPI? |
| 數據速率/采樣率 (SPS，BPS)： | 125k |
| 電壓基準： | 外部，內部 |
| 電源電壓： | 2.7 V ~ 5.25 V |
| 電流 - 電源： | 1µA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 25-UFBGA，WLCSP |
| 供應商設備封裝： | 25-WLCSP |
| 包裝： | 標準包裝 |
| 產品目錄頁面： | 779 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7877EBZ-ND - BOARD EVALUATION FOR AD7877 |
| 其它名稱： | AD7877ACBZ-REEL7DKR |
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AD7877
Data Sheet
Rev. D | Page 24 of 44
0
3796-
018
YES
NO
ONCE-ONLY
MODE?
TIMER
FINISHED?
START TIMER
NO
YES
1SEE SEQUENCER REGISTERS SECTION.
LIMIT COMPARISON
START FCD TIMER
UPDATE ALERT
ENABLE/STATUS
REGISTER
CONVERT
SELECTED CHANNEL
IS FCD
FINISHED?
NO
YES
NO
YES
NO
YES
NO
IS AVERAGING
FINISHED?
WRITE RESULT TO
REGISTERS
ALERT
SOURCE
ENABLED?
IS ACQUISITION
TIME FINISHED?
IS FCD
REQUIRED?
START ACQUISITION TIMER
OUT-OF-LIMIT?
ASSERT ALERT
OUTPUT1
YES
NO
YES
NO
VALID
SEQUENCE 1?
SELECT NEXT
CHANNEL
GO TO MODE 00
LAST CHANNEL
IN SEQUENCE?
YES
IS
SCREEN
TOUCHED?
NO
YES
NO
IS STOPACQ
SIGNAL ACTIVE?
IS STOPACQ
SIGNAL ACTIVE?
NO
YES
NO
IS
SCREEN STILL
TOUCHED?
YES
IS
SCREEN STILL
TOUCHED?
YES
NO
HOST PROGRAMS
AD7877 IN MODE 11
Figure 40. Master Mode Sequencer Operation
INTERRUPTS
Data Available Output (DAV)
The data available output (DAV) indicates that new ADC data
is available in the results registers. While the ADC is idle or is
converting, DAV is high. Once the ADC has finished converting
and new data has been written to the results registers, DAV goes
low. Taking DAV low to read the registers resets DAV to a high
condition. DAV is also reset, if a new conversion is started by
the AD7877 because the timer expired. The host should attempt
to read the results registers only when DAV is low.
03796-019
CS
DAV
AD7877
STATUS
IDLE
SETUP
BY HOST
ADC
CONVERTING
NEW DATA
AVAILABLE
HOST READS
RESULTS
IDLE
tCONV
Figure 41. Operation of DAV Output
DAV is useful as a host interrupt in master mode. In this mode,
the host can program the AD7877 to automatically perform a
sequence of conversions, and can be interrupted by DAV at the
end of each conversion sequence.
When the on-board timer is programmed to perform automatic
conversions, a limited time is available to the host to read the
results registers before another sequence of conversions begins.
The DAV signal is reset high when the timer expires, and the
host should not access the results registers while DAV is high.
Figure 42 shows the worst-case timings for reading the results
registers after DAV has gone low. The timer is set at a
minimum, and the conversion sequence includes all 11 possible
ADC channels. t1 is the time taken for acquisition and
conversion on one ADC channel. t2 shows the minimum timer
delay, that is, 1024 clock periods. t3 is the time taken to read all
11 result registers. If the host wants to read all 11 registers, then
it must do so before the timer expires. t4 is the maximum time
allowable between DAV going low and the host beginning to
read the results registers. If t4 is exceeded, then all registers
cannot be read before the start of a new conversion, and
incorrect data could be read by the host.
03796-020
DOUT
AD7877
STATUS
CHANNEL 11
CONVERSION AND
ACQUISITION
TIMER INTERVAL
CHNL
1
t1
t2
t3
t4
CS
DAV
Figure 42. Timing for Reads after DAV Goes Low
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