參數(shù)資料
型號： AD7874SQ
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System
中文描述： 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28
封裝： 0.600 INCH, HERMETIC SEALED, CERDIP-28
文件頁數(shù)： 2/16頁
文件大?。?/td> 414K
代理商： AD7874SQ
REV. C
–2–
AD7874–SPECIFICATIONS
(V
DD
= +5 V, V
SS
= –5 V, AGND = DGND = 0 V, REF IN= +3 V, f
CLK
= 2.5 MHz
external. All specifications T
MN
to T
MAX
unless otherwse noted.)
Parameter
A Version B Version S Version
Units
T est Conditions/Comments
SAMPLE-AND-HOLD
Acquisition T ime
to 0.01%
Droop Rate
–3 dB Small Signal Bandwidth
3
Aperture Delay
2
2
1
500
0
40
200
4
2
1
500
0
40
200
4
2
2
500
0
40
200
4
μ
s max
mV/ms max
kHz typ
ns min
ns max
ps typ
ns max
V
IN
= 500 mV p-p
Aperture Jitter
2, 3
Aperture Delay Matching
2
SAMPLE-AND-HOLD AND ADC
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
T otal Harmonic Distortion
Peak Harmonic or Spurious Noise
Intermodulation Distortion
2nd Order T erms
3rd Order T erms
Channel-to-Channel Isolation
2
70
–78
–78
71
–80
–80
70
–78
–78
dB min
dB max
dB max
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 29 kHz
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 29 kHz
f
= 10 kHz Sine Wave, f
SAMPLE
= 29 kHz
fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
= 29 kHz
–80
–80
–80
–80
–80
–80
–80
–80
–80
dB max
dB max
dB max
DC ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Positive Full-Scale Error
4
Negative Full-Scale Error
4
Full-Scale Error Match
Bipolar Zero Error
Bipolar Zero Error Match
12
±
1
±
1
±
5
±
5
5
±
5
4
12
±
1/2
±
1
±
5
±
5
5
±
5
4
12
±
1
±
1
±
5
±
5
5
±
5
4
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
No Missing Codes Guaranteed
Any Channel
Any Channel
Between Channels
Any Channel
Between Channels
ANALOG INPUT S
Input Voltage Range
Input Current
±
10
±
600
±
10
±
600
±
10
±
600
Volts
μ
A max
REFERENCE OUT PUT S
REF OUT
REF OUT Error @ +25
°
C
T
to T
REF OUT T emperature Coefficient
Reference Load Change
3
±
0.33
±
1
±
35
±
1
3
±
0.33
±
1
±
35
±
1
3
±
0.33
±
1
±
35
±
2
V nom
% max
% max
ppm/
°
C typ
mV max
Reference Load Current Change (0–500
μ
A)
Reference Load Should Not Be Changed During Conversion
REFERENCE INPUT
Input Voltage Range
Input Current
Input Capacitance
3
2.85/3.15
±
1
10
2.85/3.15
±
1
10
2.85/3.15
±
1
10
V min/V max 3 V
±
5%
μ
A max
pF max
LOGIC INPUT S
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
Input Capacitance, C
IN3
LOGIC OUT PUT S
Output High Voltage, V
OH
Output Low Voltage, V
OL
DB0–DB11
Floating-State Leakage Current
Floating-State Output Capacitance 10
Output Coding
2.4
0.8
±
10
10
2.4
0.8
±
10
10
2.4
0.8
±
10
10
V min
V max
μ
A max
pF max
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
V
IN
= 0 V to V
DD
4.0
0.4
4.0
0.4
4.0
0.4
V min
V max
V
DD
= 5 V
±
5%; I
SOURCE
= 40
μ
A
V
DD
= 5 V
±
5%; I
SINK
±
10
±
10
10
±
10
10
μ
A max
pF max
V
IN
= 0 V to V
DD
2s COMPLEMENT
POWER REQUIREMENT S
V
DD
V
SS
I
DD
I
SS
Power Dissipation
+5
–5
18
12
150
+5
–5
18
12
150
+5
–5
18
12
150
V nom
V nom
mA max
mA max
mW max
±
5% for Specified Performance
±
5% for Specified Performance
CS
=
RD
=
CONVST
= +5 V; T ypically 12 mA
CS
=
RD
=
CONVST
= +5 V; T ypically 8 mA
CS
=
RD
=
CONVST
= +5 V; T ypically 100 mW
NOT ES
1
T emperature ranges are as follows: A, B Versions: –40
°
C to +85
°
C; S Version: –55
°
C to +125
°
C.
2
See T erminology.
3
Sample tested @ +25
°
C to ensure compliance.
4
Measured with respect to the REF IN voltage and includes bipolar offset error.
5
For capacitive loads greater than 50 pF a series resistor is required.
Specifications subject to change without notice.
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