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參數(shù)資料
| 型號(hào)： | AD7874SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | 0.600 INCH, HERMETIC SEALED, CERDIP-28 |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大?。?/td> | 414K |
| 代理商： | AD7874SQ |
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AD7874
REV. C
–10–
MICROPROCE SSOR INT E RFACING
T he AD7874 high speed bus timing allows direct interfacing to
DSP processors as well as modern 16-bit microprocessors.
Suitable microprocessor interfaces are shown in Figures 12
through 16.
AD7874–ADSP-2100 Interface
Figure 12 shows an interface between the AD7874 and the
ADSP-2100. Conversion is initiated using a timer which allows
very accurate control of the sampling instant on all four chan-
nels. T he AD7874
INT
line provides an interrupt to the ADSP-
2100 when conversion is completed on all four channels. T he
four conversion results can then be read from the AD7874 using
four successive reads to the same memory address. T he follow-
ing instruction reads one of the four results (this instruction is
repeated four times to read all four results in sequence):
MR0 = DM(ADC)
where MR0 is the ADSP-2100 MR0 register and
ADC is the AD7874 address.
TIMER
DMA0
DMA13
DMD15
DMD0
DMS
EN
ADDR
DECODE
ADDRESS BUS
ADSP-2100
(ADSP-2101/
ADSP-2102)
* ADDITIONAL PINS OMITTED FOR CLARITY
DATA BUS
CONVST
CS
DB11
DB0
RD
INT
AD7874*
IRQn
DMRD (RD)
Figure 12. AD7874–ADSP-2100 Interface
AD7874–ADSP-2101/ADSP-2102 Interface
T he interface outlined in Figure 12 also forms the basis for an
interface between the AD7874 and the ADSP-2101/ADSP-2102.
T he READ line of the ADSP-2101/ADSP-2102 is labeled
RD
.
In this interface, the
RD
pulse width of the processor can be
programmed using the Data Memory Wait State Control Regis-
ter. T he instruction used to read one of the four results is as
outlined for the ADSP-2100.
AD7874–T MS32010 Interface
An interface between the AD7874 and the T MS32010 is shown
in Figure 13. Once again the conversion is initiated using an ex-
ternal timer and the T MS32010 is interrupted when all four
conversions have been completed. T he following instruction is
used to read the conversion results from the AD7874:
IN D,ADC
where D is Data Memory address and
ADC is the AD7874 address.
PA0
PA2
D15
D0
MEN
EN
ADDR
DECODE
ADDRESS BUS
TIMER
DATA BUS
CONVST
CS
DB11
DB0
RD
INT
AD7874*
TMS32010
*ADDITIONAL PINS OMITTED FOR CLARITY
INT
DEN
Figure 13. AD7874–TMS32010 Interface
AD7874–T MS320C25 Interface
Figure 14 shows an interface between the AD7874 and the
T MS320C25. As with the two previous interfaces, conversion is
initiated with a timer and the processor is interrupted when the
conversion sequence is completed. T he T MS320C25 does not
have a separate
RD
output to drive the AD7874
RD
input di-
rectly. T his has to be generated from the processor ST RB and
R/
W
outputs with the addition of some logic gates. T he
RD
sig-
nal is OR-gated with the MSC signal to provide the one WAIT
state required in the read cycle for correct interface timing.
Conversion results are read from the AD7874 using the follow-
ing instruction:
IN D,ADC
where D is Data Memory address and
ADC is the AD7874 address.
A0
A15
D15
D0
IS
EN
ADDR
DECODE
ADDRESS BUS
TIMER
DATA BUS
CONVST
CS
DB11
DB0
RD
INT
AD7874*
TMS320C25
*ADDITIONAL PINS OMITTED FOR CLARITY
INTn
R/W
STRB
MSC
READY
Figure 14. AD7874–TMS320C25 Interface
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