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參數(shù)資料
| 型號(hào)： | AD7865YSZ-3 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/19頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 4CHAN 5V 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 350k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 160mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個(gè)差分，雙極 |
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REV. B
AD7865
–17–
AC Linearity Plots
The plots shown in Figure 18 below show typical DNL and INL
for the AD7865.
ADC – Code
0
DNL
–
LSBs
–0.60
0
4000
8000
12000
16383
0.60
ADC – Code
0
iNL
–
LSBs
–0.60
0
4000
8000
12000
16383
0.60
Figure 18. Typical DNL and INL Plots
MICROPROCESSOR INTERFACING
The high speed parallel interface of the AD7865 allows easy
interfacing to most DSPs and microprocessors. The AD7865
interface of the AD7865 consists of the data lines (DB0 to
DB13),
CS, RD, WR, EOC and BUSY.
AD7865–ADSP-21xx Interface
Figure 19 shows an interface between the AD7865 and the
ADSP-210x. The
CONVST signal can be generated by the
ADSP-210x or from some other external source. Figure 19
shows the
CS being generated by a combination of the DMS
signal and the address bus of the ADSP-2100. In this way the
AD7865 is mapped into the data memory space of the
ADSP-210x.
The AD7865 BUSY line provides an interrupt to the ADSP-
210x when the conversion sequence is complete on all the
selected channels. The conversion results can then be read from
the AD7865 using successive read operations. Alternately, one
can use the
EOC pulse to interrupt the ADSP-210x when the
conversion on each channel is complete when reading between
each conversion in the conversion sequence (Figure 8). The
AD7865 is read using the following instruction
MR0 = DM(ADC)
where MR0 is the ADSP-210x MR0 register and ADC is the
AD7865 address.
CS
RD
WR
BUSY
CONVST
DB0–DB13
AD7865
VIN1
VIN2
VIN3
VIN4
DT1/F0
IRQn
RD
WR
D0–D13
DMS
A0–A13
ADSP-21xx
ADDRESS
DECODE
Figure 19. AD7865–ADSP-21xx Interface
AD7865–TMS320C5x Interface
Figure 20 shows an interface between the AD7865 and the
TMS320C5x. As with the previous interfaces, conversion can be
initiated from the TMS320C5x or from an external source and
the processor is interrupted when the conversion sequence is
completed. The
CS signal to the AD7865 derived from the DS
signal and a decode of the address bus. This maps the AD7865
into external data memory. The
RD signal from the TMS320 is
used to enable the ADC data onto the data bus. The AD7865
has a fast parallel bus so there are no wait state requirements.
The following instruction is used to read the conversion results
from the AD7865:
IN D,ADC
where D is Data Memory address and ADC is the AD7865
address.
PA0
INTn
DS
TMS320C5x
CS
RD
WR
BUSY
CONVST
DB0–DB13
AD7865
VIN1
VIN2
VIN3
VIN4
RD
WR
D0–D13
A0–A13
ADDRESS
DECODE
Figure 20. AD7865–TMS320C5x Interface
AD7865–MC68000 Interface
An interface between the AD7865 and the MC68000 is shown
in Figure 21. The conversion can be initiated from the MC68000
or from an external source. The AD7865 BUSY line can be
used to interrupt the processor or, alternatively, software delays
can ensure that conversion has been completed before a read to
the AD7865 is attempted. Because of the nature of its inter-
rupts, the 68000 requires additional logic (not shown in Figure
21) to allow it to be interrupted correctly. For further informa-
tion on 68000 interrupts, consult the 68000 users manual.
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