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參數(shù)資料
| 型號： | AD7865YSZ-3 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 4CHAN 5V 44-MQFP |
| 標準包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 350k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 160mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應商設備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個差分，雙極 |
REV. B
AD7865
–7–
Pin
Mnemonic
Description
24
VREF
Reference Input/Output. This pin provides access to the internal reference (2.5 V
± 20 mV)
and also allows the internal reference to be overdriven by an external reference source (2.5 V
± 5%). A 0.1 F decoupling capacitor should be connected between this pin and AGND.
25
AVDD
Analog Positive Supply Voltage, 5.0 V
± 5%. A 0.1 F decoupling capacitor should be con-
nected between this pin and AGND.
26
AGND
Analog Ground. General Analog Ground. This AGND pin should be connected to the system’s
AGND plane.
27–34
DB13–DB6
Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 6. Three-state TTL outputs.
Output coding is twos complement for AD7865-1 and AD7865-3, and straight binary for
AD7865-2.
35
DVDD
Positive Supply Voltage for Digital section, 5.0 V
± 5%. A 0.1 F decoupling capacitor should
be connected between this pin and AGND. Both DVDD and AVDD should be externally tied
together.
36
VDRIVE
This pin provides the positive supply voltage for the output drivers (DB0 to DB13), BUSY,
EOC and FRSTDATA. It is normally tied to DV
DD. VDRIVE should be decoupled with a
0.1
F capacitor. It allows improved performance when reading during the conversion
sequence. Also, the output data drivers may be powered by a 3 V
± 10% supply to facilitate
interfacing to 3 V processors and DSPs.
37
DGND
Digital Ground. Ground reference for Digital circuitry. This DGND pin should be connected
to the system’s DGND plane. The system’s DGND and AGND planes should be connected
together at one point only, preferably at an AGND pin.
38, 39
DB5, DB4
Data Bit 5 to Data Bit 4. Three-state TTL outputs.
40–43
DB3–DB0
Data Bit 3 to Data Bit 0. Bidirectional data pins. When a read operation takes place, these
pins are three-state TTL outputs. The channel select register is programmed with the data on
the DB0–DB3 pins with standard
CS and WR signals. DB0 represents Channel 1 and DB3
represents Channel 4.
44
EOC
End-of-Conversion. Active low logic output indicating conversion status. The end of each
conversion in a conversion sequence is indicated by a low going pulse on this line.
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