Limit at TMIN, TMAX (A, B Versi" />
參數(shù)資料
型號(hào)： AD7859BSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 23/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 8CHAN LP 44-MQFP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 200k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 30mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 托盤
輸入數(shù)目和類型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)偽差分，單極；4 個(gè)偽差分，雙極
AD7859/AD7859L
REV. A
–4–
Limit at TMIN, TMAX
(A, B Versions)
Parameter
5 V
3 V
Units
Description
fCLKIN
2
500
kHz min
Master Clock Frequency
4
MHz max
1.8
MHz max
L Version
t1
3
100
ns min
CONVST
Pulse Width
t2
50
90
ns max
CONVST
to BUSY
↑ Propagation Delay
tCONVERT
4.5
s max
Conversion Time = 18 tCLKIN
10
s max
L Version 1.8 MHz CLKIN. Conversion Time = 18 tCLKIN
t3
15
ns min
HBEN to RD Setup Time
t4
5
ns min
HBEN to RD Hold Time
t5
0
ns min
CS
to RD to Setup Time
t6
0
ns min
CS
to RD Hold Time
t7
55
ns min
RD
Pulse Width
t8
4
50
ns max
Data Access Time After RD
t9
5
ns min
Bus Relinquish Time After RD
40
ns max
Bus Relinquish Time After RD
t10
60
70
ns min
Minimum Time Between Reads
t11
0
ns min
HBEN to WR Setup Time
t12
5
ns max
HBEN to WR Hold Time
t13
0
ns min
CS
to WR Setup Time
t14
0
ns max
CS
to WR Hold Time
t15
55
70
ns min
WR
Pulse Width
t16
10
ns min
Data Setup Time Before WR
t17
5
ns min
Data Hold Time After WR
t18
4
1/2 tCLKIN
ns min
New Data Valid Before Falling Edge of BUSY
t19
2.5 tCLKIN
ns max
CS
↑ to BUSY ↑ in Calibration Sequence
tCAL
6
31.25
ms typ
Full Self-Calibration Time, Master Clock Dependent (125013
tCLKIN)
tCAL1
6
27.78
ms typ
Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111124 tCLKIN)
tCAL2
6
3.47
ms typ
System Offset Calibration Time, Master Clock Dependent
(13889 tCLKIN)
NOTES
1Sample tested at +25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 V.
2Mark/Space ratio for the master clock input is 40/60 to 60/40.
3The CONVST pulse width will here only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-
Down section).
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5t
9 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 9, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8 MHz master clock.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1
(AVDD = DVDD = +3.0 V to +5.5 V; fCLKIN = 4 MHz for AD7859 and 1.8 MHz for AD7859L;
TA = TMIN to TMAX, unless otherwise noted)
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相關(guān)代理商/技術(shù)參數(shù)
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AD7859L 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCs
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AD7859LAS3 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V to 5 V Single Supply, 200 kSPS8-Channel, 12-Bit Sampling ADCs
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