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參數資料
| 型號： | AD7856ARSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 8/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 8CHAN 5V 24SSOP |
| 標準包裝： | 1 |
| 位數： | 14 |
| 采樣率（每秒）： | 285k |
| 數據接口： | 8051，QSPI?，串行，SPI? µP |
| 轉換器數目： | 2 |
| 功率耗散（最大）： | 89.25mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 24-SSOP |
| 包裝： | 管件 |
| 輸入數目和類型： | 8 個單端，單極；4 個偽差分，單極 |
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AD7856
–16–
REV. A
ANALOG INPUT
The equivalent circuit of the analog input section is shown in
Figure 11. During the acquisition interval the switches are both
in the track position and the AIN(+) charges the 20 pF capaci-
tor through the 125
resistance. On the rising edge of CONVST
switches SW1 and SW2 go into the hold position retaining
charge on the 20 pF capacitor as a sample of the signal on
AIN(+). The AIN(–) is connected to the 20 pF capacitor, and
this unbalances the voltage at node A at the input of the com-
parator. The capacitor DAC adjusts during the remainder of the
conversion cycle to restore the voltage at node A to the correct
value. This action transfers a charge, representing the analog
input signal, to the capacitor DAC which in turn forms a digital
representation of the analog input signal. The voltage on the
AIN(–) pin directly influences the charge transferred to the
capacitor DAC at the hold instant. If this voltage changes dur-
ing the conversion period, the DAC representation of the analog
input voltage will be altered. Therefore it is most important that
the voltage on the AIN(–) pin remains constant during the con-
version period. Furthermore, it is recommended that the AIN(–)
pin is always connected to AGND or to a fixed dc voltage.
CAPACITOR
DAC
COMPARATOR
HOLD
TRACK
SW2
NODE A
20pF
SW1
TRACK
HOLD
125
AIN(+)
AIN(–)
CREF2
125
Figure 11. Analog Input Equivalent Circuit
Acquisition Time
The track and hold amplifier enters its tracking mode on the
falling edge of the BUSY signal. The time required for the track
and hold amplifier to acquire an input signal will depend on
how quickly the 20 pF input capacitance is charged. The acqui-
sition time is calculated using the formula:
tACQ = 10
× (R
IN + 125
) × 20 pF
where RIN is the source impedance of the input signal, and
125
, 20 pF is the input RC.
DC/AC Applications
For dc applications high source impedances are acceptable
provided there is enough acquisition time between conversions
to charge the 20 pF capacitor. The acquisition time can be
calculated from the above formula for different source imped-
ances. For example, with RIN = 5 k the required acquisition
time will be 1025 ns.
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC low-
pass filter on the AIN(+) pin as shown in Figure 13. In applica-
tions where harmonic distortion and signal-to-noise ratio are
critical, the analog input should be driven from a low impedance
source. Large source impedances will significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp will be a func-
tion of the particular application.
When no amplifier is used to drive the analog input the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of total harmonic
distortion (THD) that can be tolerated. The THD will increase
as the source impedance increases and performance will de-
grade. Figure 12 shows a graph of the total harmonic distortion
versus analog input signal frequency for different source imped-
ances. With the setup as in Figure 13, the THD is at the –90 dB
level. With a source impedance of 1 k
and no capacitor on the
AIN(+) pin, the THD increases with frequency.
THD
–
dB
INPUT FREQUENCY – kHz
–50
–60
–110
–100
–80
–90
–70
1
166
10
20
50
80
RIN = 560
RIN = 10 , 10nF
AS IN FIGURE 13
140
120
100
THD VS. FREQUENCY FOR DIFFERENT
SOURCE IMPEDANCES
Figure 12. THD vs. Analog Input Frequency
In a single supply application (5 V), the V+ and V– of the op
amp can be taken directly from the supplies to the AD7856
which eliminates the need for extra external power supplies.
When operating with rail-to-rail inputs and outputs, at frequen-
cies greater than 10 kHz care must be taken in selecting the
particular op amp for the application. In particular for single
supply applications the input amplifiers should be connected in
a gain of –1 arrangement to get the optimum performance.
Figure 13 shows the arrangement for a single supply application
with a 50
and 10 nF low-pass filter (cutoff frequency 320 kHz)
on the AIN(+) pin. Note that the 10 nF is a capacitor with good
linearity to ensure good ac performance. Recommended single
supply op amp is the AD820.
AD820
0.1 F
10 F
V+
V–
10k
50
10nF
(NPO)
TO AIN(+)
OF
AD7856
VIN
(0 TO VREF)
VREF
10k
+5V
IC1
Figure 13. Analog Input Buffering
Input Range
The analog input range for the AD7856 is 0 V to VREF. The
AIN(–) pin on the AD7856 can be biased up above AGND, if
required. The advantage of biasing the lower end of the analog
input range away from AGND is that the user does not need to
have the analog input swing all the way down to AGND. This
has the advantage in true single supply applications that the
input amplifier does not need to swing all the way down to
AGND. The upper end of the analog input range is shifted up
by the same amount. Care must be taken so that the bias ap-
plied does not shift the upper end of the analog input above the
AVDD supply. In the case where the reference is the supply,
AVDD, the AIN(–) must be tied to AGND.
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