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參數(shù)資料
| 型號： | AD7856ARSZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 8CHAN 5V 24SSOP |
| 標準包裝： | 500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 285k |
| 數(shù)據(jù)接口： | 8051，QSPI?，串行，SPI? µP |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 89.25mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 24-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；4 個偽差分，單極 |
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AD7856
–20–
REV. A
internal switch opens to provide a high impedance discharge
path for the reference capacitor during power-down—see Figure
23. An added advantage of the low charge leakage from the
reference capacitor during power-down is that even though the
reference is being powered down between conversions, the
reference capacitor holds the reference voltage to within
0.5 LSBs with throughput rates of 100 samples/second and over
with a full power-down between conversions. A high input im-
pedance op amp like the AD707 should be used to buffer this
reference capacitor if it is being used externally. Note, if the
AD7856 is left in its power-down state for more than 100 ms,
the charge on CREF will start to leak away and the power-up
time will increase. If this long power-up time is a problem, the
user can use a partial power-down for the last conversion so the
reference remains powered up.
AD7856
REFIN/REFOUT
EXTERNAL
CAPACITOR
SWITCH OPENS
DURING POWER-DOWN
BUF
ON-CHIP
REFERENCE
TO OTHER
CIRCUITRY
Figure 23. On-Chip Reference During Power-Down
POWER VS. THROUGHPUT RATE
The main advantage of a full power-down after a conversion is
that it significantly reduces the power consumption of the part
at lower throughput rates. When using this mode of operation
the AD7856 is only powered up for the duration of the conver-
sion. If the power-up time of the AD7856 is taken to be 5
s
and it is assumed that the current during power up is 12 mA
typ, then power consumption as a function of throughput can
easily be calculated. The AD7856 has a conversion time of
3.5
s with a 6 MHz external clock. This means the AD7856
consumes 12 mA typ, (or 60 mW typ VDD = 5 V) for 8.5
s in
every conversion cycle if the device is powered down at the end
of a conversion. If the throughput rate is 1 kSPS, the cycle time
is 1000
s and the average power dissipated during each cycle is
(8.5/1000)
× (60 mW) = 510 W. The graph, Figure 24, shows
the power consumption of the AD7856 as a function of through-
put. Table VII lists the power consumption for various through-
put rates.
Table VII. Power Consumption vs. Throughput
Throughput Rate
Power
1 kSPS
510
W
10 kSPS
5.1 mW
The AD7856 powers up from a full hardware or software
power-down in 5
s typ. This limits the throughput which the
part is capable of to 93 kSPS for the K grade and 113 kSPS for
the A grade when powering down between conversions. Figure
22 shows how power-down between conversions is implemented
using the
CONVST pin. The user first selects the power-down
between conversions option by using the
SLEEP pin and the
power management bits, PMGT1 and PMGT0, in the control
register, (see last section). In this mode the AD7856 automati-
cally enters a full power-down at the end of a conversion, i.e.,
when BUSY goes low. The falling edge of the next
CONVST
pulse causes the part to power up. Assuming the external refer-
ence is left powered up, the AD7856 should be ready for normal
operation 5
s after this falling edge. The rising edge of CONVST
initiates a conversion so the
CONVST pulse should be at least
5
s wide. The part automatically powers down on completion
of the conversion.
5 s
3.5 s
tCONVERT
POWER-UP
TIME
NORMAL
OPERATION
FULL
POWER-DOWN
POWER-UP
TIME
START CONVERSION ON RISING EDGE
POWER-UP ON FALLING EDGE
CONVST
BUSY
Figure 22. Power-Up Timing When Using
CONVST Pin
NOTE: Where the software
CONVST is used, the part must be
powered up in software with an extra write setting PMGT1 = 0
and PMGT0 = 1 before a conversion is initiated in the next
write. Automatic partial power-down after a calibration is not
possible; the part must be powered down manually. If software
calibrations are to be used when operating in the partial power-
down mode, then three separate writes are required. The first
initiates the type of calibration required, the second write pow-
ers the part down into partial power-down mode, while the third
write powers the part up again before the next calibration com-
mand is issued.
Using the Internal (On-Chip) Reference
As in the case of an external reference, the AD7856 can power-
up from one of two conditions, power-up after the supplies are
connected or power-up from hardware/software power-down.
When using the on-chip reference and powering up when AVDD
and DVDD are first connected, it is recommended that the power-
up calibration mode be disabled as explained above. When using
the on-chip reference, the power-up time is effectively the time
it takes to charge up the external capacitor on the REFIN/REFOUT
pin. This time is given by the equation:
tUP = 10
× R × C
where R
150 k and C = external capacitor.
The recommended value of the external capacitor is 100 nF;
this gives a power-up time of approximately 150 ms before a
calibration is initiated and normal operation should commence.
When CREF is fully charged, the power-up time from a hardware
or software power-down reduces to 5
s. This is because an
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| AD7856ARZ | 功能描述:IC ADC 14BIT 8CHAN 5V 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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| AD7856KR | 制造商:Analog Devices 功能描述:ADC Single SAR 285ksps 14-bit Serial 24-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:8 CH. 14-BIT 300 KSPS ADC I.C. - Bulk |
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