參數(shù)資料
型號(hào)： AD7854LARSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT PARALLEL LP 28SSOP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 12
采樣率（每秒）： 100k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 30mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)偽差分，單極；1 個(gè)偽差分，雙極
AD7854/AD7854L
–22–
REV. B
System Gain and Offset Interaction
The architecture of the AD7854/AD7854L leads to an interac-
tion between the system offset and gain errors when a system
calibration is performed. Therefore it is recommended to perform
the cycle of a system offset calibration followed by a system gain
calibration twice. When a system offset calibration is performed,
the system offset error is reduced to zero. If this is followed by a
system gain calibration, then the system gain error is now zero,
but the system offset error is no longer zero. A second sequence
of system offset error calibration followed by a system gain cali-
bration is necessary to reduce system offset error to below the
12-bit level. The advantage of doing separate system offset and
system gain calibrations is that the user has more control over
when the analog inputs need to be at the required levels, and the
CONVST signal does not have to be used.
Alternatively, a system (gain + offset) calibration can be per-
formed. At the end of one system (gain + offset) calibration, the
system offset error is zero, while the system gain error is reduced
from its initial value. Three system (gain + offset) calibrations
are required to reduce the system gain error to below the 12-bit
error level. There is never any need to perform more than three
system (gain + offset) calibrations.
In bipolar mode the midscale error is adjusted for an offset cali-
bration and the positive full-scale error is adjusted for the gain
calibration; in unipolar mode the zero-scale error is adjusted for
an offset calibration and the positive full-scale error is adjusted
for a gain calibration.
System Calibration Timing
The timing diagram in Figure 33 is for a software full system
calibration. It may be easier in some applications to perform
separate gain and offset calibrations so that the
CONVST bit in
the control register does not have to be programmed in the
middle of the system calibration sequence. Once the write to the
control register setting the bits for a full system calibration is
completed, calibration of the internal DAC is initiated and the
BUSY line goes high. The full-scale system voltage should be
applied to the analog input pins, AIN(+) and AIN(–) at the start
of calibration. The BUSY line goes low once the DAC and
system gain calibration are complete. Next the system offset
voltage should be applied across the AIN(+) and AIN(–) pins
for a minimum setup time (tSETUP) of 100 ns before the rising
edge of
CS. This second write to the control register sets the
CONVST bit to 1 and at the end of this write operation the
BUSY signal is triggered high (note that a
CONVST pulse can
be applied instead of this second write to the control register).
The BUSY signal is low after a time tCAL2 when the system offset
calibration section is complete. The full system calibration is now
complete.
The timing for a system (gain + offset) calibration is very similar
to that of Figure 33, the only difference being that the time tCAL1 is
replaced by a shorter time of the order of tCAL2 as the internal
DAC is not calibrated. The BUSY signal signifies when the gain
calibration is finished and when the part is ready for the offset
calibration.
CONVST BIT SET
TO 1 IN CONTROL
REGISTER
t23
DATA LATCHED INTO
CONTROL REGISTER
Hi-Z
tCAL1
t23
tSETUP
VOFFSET
VSYSTEM FULL SCALE
DATA
VALID
CS
WR
DATA
BUSY
AIN
DATA
VALID
tCAL2
Figure 33. Timing Diagram for Full System Calibration
The timing diagram for a system offset or system gain calibra-
tion is shown in Figure 34. Here again a write to the control
register initiates the calibration sequence. At the end of the con-
trol register write operation the BUSY line goes high and it stays
high until the calibration sequence is finished. The analog input
should be set at the correct level for a minimum setup time
(tSETUP) of 100 ns before the CS rising edge and stay at the cor-
rect level until the BUSY signal goes low.
t23
Hi-Z
DATA LATCHED INTO
CONTROL REGISTER
tSETUP
tCAL2
DATA
VALID
VSYSTEM FULL SCALE OR VOFFSET
CS
WR
DATA
BUSY
AIN
Figure 34. Timing Diagram for System Gain or System
Offset Calibration
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參數(shù)描述
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