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參數(shù)資料
| 型號： | AD7841BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/13頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT OCTAL VOUT 44-MQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 800 |
| 設置時間： | 31µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 303mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應商設備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，單極；8 電壓，雙極 |
| 采樣率（每秒）： | 32k |
| 配用： | EVAL-AD7841EBZ-ND - BOARD EVAL FOR AD7841 |
AD7841
–10–
DUTGND Voltage Range
During power-on, the VOUT pins of the AD7841 are connected
to the relevant DUTGND pins via G5 and the 14 k
thin-film
resistor. The DUTGND potential must obey the max ratings at
all times. Thus, the voltage at DUTGND must always be within
the range VSS – 0.3 V, VDD + 0.3 V. However, in order that the
voltages at the VOUT pins of the AD7841 stay within
±2 V of the
relevant DUTGND potential during power-on, the voltage
applied to DUTGND should also be kept within the range
GND – 2 V, GND + 2 V.
Once the AD7841 has powered on and the on-chip amplifiers
have settled, any voltage that is now applied to the DUTGND
pin is subtracted from the DAC output, which has been gained
up by a factor of two. Thus, for specified operation, the maximum
voltage that can be applied to the DUTGND pin increases to the
maximum allowable 2 VREF(+) voltage, and the minimum volt-
age that can be applied to DUTGND is the minimum 2 VREF(–)
voltage. After the AD7841 has fully powered on, the outputs
can track any DUTGND voltage within this minimum/maxi-
mum range.
Power Supply Sequencing
When operating the AD7841, it is important that ground be
connected at all times to avoid high current states. The recom-
mended power-up sequence is VDD/VSS followed by VCC. If VCC
can exceed VDD on power-up, the diode scheme shown in the
absolute maximum ratings section will ensure protection. The
reference inputs and digital inputs should be powered up last.
Should the references exceed VDD/VSS on power-up, current
limiting resistors should be inserted in series with the reference
inputs to limit the current to 20 mA. Logic inputs should not be
applied before VCC. Current limiting resistors (470
) in series
with the logic inputs should be inserted if these inputs come up
before VCC.
MICROPROCESSOR INTERFACING
Interfacing the AD7841—16-Bit Interface
The AD7841 can be interfaced to a variety of 16-bit micro-
controllers or DSP processors. Figure 10 shows the AD7841
interfaced to a generic 16-bit microcontroller/DSP processor.
The lower address lines from the processor are connected to A0,
A1 and A2 on the AD7841 as shown. The upper address lines
are decoded to provide a chip select signal or an
LDAC signal
for the AD7841. The fast interface timing of the AD7841 allows
direct interface to a wide variety of microcontrollers and DSPs
as shown in Figure 10.
AD7841
CONTROLLER/
DSP PROCESSOR*
ADDRESS
DECODE
D13
D0
DATA
BUS
UPPER BITS OF
ADDRESS BUS
A2
A1
A0
R/
W
*ADDITIONAL PINS OMITTED FOR CLARITY
D13
D0
CS
LDAC
A2
A1
A0
WR
Figure 10. Parallel Interface
APPLICATIONS
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD7841 is mounted should be designed such that the analog
and digital sections are separated and confined to certain areas
of the board. This facilitates the use of ground planes that can
be easily separated. A minimum etch technique is generally best
for ground planes as it gives the best shielding. Digital and ana-
log ground planes should be joined at only one place. The GND
pin of the AD7841 should be connected to the AGND of the
system. If the AD7841 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only, a star ground point that should be
established as close as possible to the AD7841.
Digital lines running under the device should be avoided as
these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7841 to avoid noise
coupling. The power supply lines of the AD7841 should use as
large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line. Fast
switching signals like clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board and
should never be run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro-
strip technique is by far the best but not always possible with a
double sided board. In this technique, the component side of
the board is dedicated to ground plane while signal traces are
placed on the solder side.
REV. B
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