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參數(shù)資料
| 型號： | AD783JRZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP SAMPLE HOLD LP 5MA 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 采樣和保持 |
| 電路數(shù)： | 1 |
| -3db帶寬： | 15MHz |
| 電流 - 輸入偏壓： | 100nA |
| 電流 - 電源： | 9.5mA |
| 電流 - 輸出 / 通道： | 5mA |
| 電壓 - 電源，單路/雙路(±)： | ±4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 773 (CN2011-ZH PDF) |
AD783
REV. A
–6–
DYNAMIC PERFORMANCE
The AD783 is compatible with 12-bit A-to-D converters in
terms of both accuracy and speed. The fast acquisition time, fast
hold settling time and good output drive capability allow the
AD783 to be used with high speed, high resolution A-to-D
converters like the AD671 and AD7586. The AD783’s fast
acquisition time provides high throughput rates for multichannel
data acquisition systems. Typically, the AD783 can acquire a
5 V step in less than 250 ns. Figure 1 shows the settling
accuracy as a function of acquisition time.
0.08
0.06
0.04
0.02
0
250
500
ACQUISITION TIME – ns
V
ACQUISITION
ACCURACY
–
%
OUT
Figure 1. VOUT Settling vs. Acquisition Time
The hold settling determines the required time, after the hold
command is given, for the output to settle to its final specified
accuracy. The typical settling behavior of the AD783 is 150 ns.
The settling time of the AD783 is sufficiently fast to allow the
SHA, in most cases, to directly drive an A-to-D converter
without the need for an added “start convert” delay.
HOLD MODE OFFSET
The dc accuracy of the AD783 is determined primarily by the
hold mode offset. The hold mode offset refers to the difference
between the final held output voltage and the input signal at the
time the hold command is given. The hold mode offset arises
from a voltage error introduced onto the hold capacitor by
charge injection of the internal switches. The nominal hold
mode offset is specified for a 0 V input condition. Over the in-
put range of –2.5 V to +2.5 V, the AD783 is also characterized
for an effective gain error and nonlinearity of the held value, as
shown in Figure 2. As indicated by the AD783 specifications,
the hold mode offset is very stable over temperature.
NONLINEARITY
GAIN ERROR
V
, VOLTS
IN
–2.5
+2.5
+1
HOLD MODE OFFSET
–1
(VOUT HOLD – VIN), mV
Figure 2. Hold Mode Offset, Gain Error and Nonlinearity
For applications where it is important to obtain zero offset, the
hold mode offset may be nulled externally at the input to the
A-to-D converter. Adjustment of the offset may be accom-
plished through the A-to-D itself or by an external amplifier
with offset nulling capability (e.g., AD711). The offset will
change less than 0.5 mV over the specified temperature range.
SUPPLY DECOUPLING AND GROUNDING
CONSIDERATIONS
As with any high speed, high resolution data acquisition system,
the power supplies should be well regulated and free from
excessive high frequency noise (ripple). The supply connection
to the AD783 should also be capable of delivering transient
currents to the device. To achieve the specified accuracy and
dynamic performance, decoupling capacitors must be placed
directly at both the positive and negative supply pins to com-
mon. Ceramic type 0.1
F capacitors should be connected from
VCC and VEE to common.
ANALOG
P.S.
DIGITAL
P.S.
+5V
C
–5V
C
+5V
0.1
F 0.1F1F1F1F
AD783
DIGITAL
DATA
OUTPUT
SIGNAL GROUND
INPUT
ANALOG-TO-DIGITAL
CONVERTER
Figure 3. Basic Grounding and Decoupling Diagram
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| AD7840ARS | 功能描述:IC DAC 14BIT LOW POWER 5V 24SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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