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參數(shù)資料
| 型號： | AD7836ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT QUAD LC2MOS 44MQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設(shè)置時間： | 16µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 460mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 62.5k |
AD7836
–6–
REV. A
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the max-
imum deviation from a straight line passing through the endpoints
of the DAC transfer function. It is measured after adjusting for
zero error and full-scale error and is normally expressed in Least
Significant Bits or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
DC Crosstalk
Although the common input reference voltage signals are inter-
nally buffered, small IR drops in the individual DAC reference
inputs across the die can mean that an update to one channel
can produce a dc output change in one or other of the channel
outputs.
The four DAC outputs are buffered by op amps that share com-
mon VDD and VSS power supplies. If the dc load current changes
in one channel (due to an update), this can result in a further dc
change in one or other channel outputs. This effect is most ob-
vious at high load currents and reduces as the load currents are
reduced. With high impedance loads the effect is virtually
unmeasurable.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected into the analog output when
the inputs change state. It is specified as the area of the glitch in
nV-secs. It is measured with VREF(+) = +5 V and VREF(–) = –5 V
and the digital inputs toggled between 1FFFHEX and 8000H.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DACs reference input that appears at the output
of the other DAC. It is expressed in dBs.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is defined as the glitch impulse that ap-
pears at the output of one converter due to both the digital
change and subsequent analog O/P change at another converter.
It is specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the VOUT
pins. This noise is digital feedthrough.
DC Output Impedance
This is the effective output source resistance. It is dominated by
package lead resistance.
Full-Scale Error
This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s
loaded into the DAC latch, should be 2 VREF(+) – 1 LSB. Full-
scale error does not include zero-scale error.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC latch. Ideally the output voltage,
with all 0s in the DAC latch should be equal to 2 VREF(–). Zero-
scale error is mainly due to offsets in the output amplifier.
Gain Error
Gain Error is defined as (Full-Scale Error) – (Zero-Scale Error).
GENERAL DESCRIPTION
DAC Architecture—General
Each channel consists of a segmented 14-bit R-2R voltage-mode
DAC. The full-scale output voltage range is equal to twice the
reference span of VREF(+) – VREF(–). The DAC coding is
straight binary; all 0s produces an output of 2 VREF(–); all 1s
produces an output of 2 VREF(+) – 1 LSB.
The analog output voltage of each DAC channel reflects the
contents of its own DAC latch. Data is transferred from the ex-
ternal bus to the input register of each DAC latch on a per
channel basis. The AD7836 has a feature whereby using the A2
pin, data can be transferred from the input data bus to all four
input registers simultaneously.
Bringing the CLR line low switches all the signal outputs,
VOUTA to VOUTD, to the voltage level on the DUTGND pin.
When CLR signal is brought back high the output voltages from
the DACs will reflect the data stored in the relevant DAC
registers.
Data Loading to the AD7836
Data is loaded into the AD7836 in straight parallel 14-bit wide
words.
The DAC output voltages, VOUTA–VOUTD are updated to
reflect new data in the DAC input registers.
The actual DAC input register that is being written to is deter-
mined by the logic levels present on the devices address lines, as
shown in Table I.
Table I. Address Line Truth Table
A2
A1
A0
DAC Selected
0
DATA REG A (DAC A)
0
1
DATA REG B (DAC B)
0
1
0
DATA REG C (DAC C)
0
1
DATA REG D (DAC D)
1
0
DATA REG E
1
DATA REG A–D
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