參數(shù)資料
型號: AD7836
廠商: Analog Devices, Inc.
英文描述: Quad 14-Bit DAC(14位四通道D/A轉(zhuǎn)換器)
中文描述: 四路14位DAC(14位四通道的D / A轉(zhuǎn)換器)
文件頁數(shù): 1/12頁
文件大?。?/td> 168K
代理商: AD7836
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
LC
2
MOS
Quad 14-Bit DAC
AD7836
Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
Four 14-Bit DACs in One Package
Voltage Outputs
Separate Offset Adjust for Each Output
Reference Range of
6
5 V
Maximum Output Voltage Range of
6
10 V
Clear Function to User-Defined Code
44-Pin PQFP Package
APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation
GE NE RAL DE SCRIPT ION
T he AD7836 contains four 14-bit DACs on one monolithic
chip. It has output voltages with a full-scale range of
±
10 V
from reference voltages of
±
5 V.
T he AD7836 accepts 14-bit parallel loaded data from the exter-
nal bus into one of the input latches under the control of the
WR
,
CS
and DAC channel address pins, A0–A2.
T he DAC outputs are updated individually, on reception of new
data. In addition, the SEL input can be used to apply the user
programmed value in DAC Register E to all DACs, thus setting
all DAC output voltages to the same level. T he contents of the
DAC data registers are not affected by the SEL input.
Each DAC output is buffered with a gain of two amplifier into
which an external DAC offset voltage can be inserted via the
DUT GNDx pins.
T he AD7836 is available in a 44-pin PQFP package.
FUNCT IONAL BLOCK DIAGRAM
DATA
REG
A
DATA
REG
B
MUX
DAC A
MUX
MUX
MUX
DATA
REG
C
DATA
REG
D
DATA
REG
E
X1
X1
X1
X1
X1
X1
X1
X1
R
R
R
R
R
R
R
R
INPUT
BUFFER
AD7836
ADDRESS
DECODE
DUTGND D
DUTGND C
V
OUT
D
DUTGND B
V
OUT
C
DUTGND A
V
OUT
B
V
OUT
A
A0
A1
A2
DB0
WR
CS
DB13
V
CC
V
SS
V
DD
V
REF
(+)A
CLR
SEL
AGND
DGND
14
14
14
14
14
DAC B
DAC D
V
REF
(–)A
V
REF
(+)B
V
REF
(–)B
DAC B
V
REF
(+)D
V
REF
(–)D
V
REF
(+)C
V
REF
(–)C
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