參數(shù)資料
型號(hào)： AD7829BRUZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 10/28頁
文件大?。?/td> 0K
描述： IC ADC 8BIT 8CHAN 2MSPS 28TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 8
采樣率（每秒）： 2M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 36mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極
AD7822/AD7825/AD7829
Rev. C | Page 18 of 28
MICROPROCESSOR INTERFACING
The parallel port on the AD7822/AD7825/AD7829 allows
the ADCs to be interfaced to a range of many different micro-
controllers. This section explains how to interface the AD7822/
AD7825/AD7829 with some of the more common microcontroller
parallel interface protocols.
AD7822/AD7825/AD7829 TO 8051
Figure 27 shows a parallel interface between the AD7822/AD7825/
AD7829 and the 8051 microcontroller. The EOCsignal on the
AD7822/AD7825/AD7829 provides an interrupt request to the
8051 when a conversion ends and data is ready. Port 0 of the 8051
can serve as an input or output port; or, as in this case when used
together with the address latch enable (ALE) of the 8051, can be
used as a bidirectional low order address and data bus. The ALE
output of the 8051 is used to latch the low byte of the address
during accesses to the device, while the high order address byte
is supplied from Port 2. Port 2 latches remain stable when the
AD7822/AD7825/ AD7829 are addressed because they do not
have to be turned around (set to 1) for data input, as is the case
for Port 0.
AD0 TO AD7
ALE
A8 TO A15
RD
INT
80511
LATCH
DECODER
DB0 TO DB7
RD
EOC
CS
1ADDITIONAL PINS OMITTED FOR CLARITY.
AD7822/
AD7825/
AD78291
013
21-
0
28
Figure 27. Interfacing to the 8051
AD7822/AD7825/AD7829 TO PIC16C6x/PIC16C7x
Figure 28 shows a parallel interface between the AD7822/
AD7825/AD7829 and the PIC16C64/PIC16C65/PIC16C74.
The EOC signal on the AD7822/AD7825/AD7829 provides an
interrupt request to the microcontroller when a conversion
begins. Of the PIC16C6x/PIC16C7x range of microcontrollers,
only the PIC16C64/PIC16C65/PIC16C74 can provide the
option of a parallel slave port. Port D of the microcontroller
operates as an 8-bit wide parallel slave port when Control Bit
PSPMODE in the TRISE register is set. Setting PSPMODE
enables Port Pin RE0 to be the RD output and RE2 to be the CS
(chip select) output. For this functionality, the corresponding
data direction bits of the TRISE register must be configured as
outputs (reset to 0). See the PIC16C6x/PIC16C7x microcontroller
user manual.
PSP0 TO PSP7
RD
INT
PIC16C6x/7x1
DB0 TO DB7
RD
EOC
CS
1ADDITIONAL PINS OMITTED FOR CLARITY.
CS
AD7822/
AD7825/
AD78291
01321-
029
Figure 28. Interfacing to the PIC16C6x/ PIC16C7x
AD7822/AD7825/AD7829 TO ADSP-21xx
Figure 29 shows a parallel interface between the AD7822/
AD7825/AD7829 and the ADSP-21xx series of DSPs. As before,
the EOC signal on the AD7822/AD7825/AD7829 provides an
interrupt request to the DSP when a conversion ends.
D7 TO D0
RD
IRQ
ADSP-21xx1
DB0 TO DB7
RD
EOC
CS
1ADDITIONAL PINS OMITTED FOR CLARITY.
DMS
EN
ADDRESS
DECODE
LOGIC
A13 TO A0
AD7822/
AD7825/
AD78291
01321-
030
Figure 29. Interfacing to the ADSP-21xx
INTERFACING MULTIPLEXER ADDRESS INPUTS
Figure 30 shows a simplified interfacing scheme between the
AD7825/AD7829 and any microprocessor or microcontroller,
which facilitates easy channel selection on the ADCs. The multi-
plexer address is latched on the falling edge of the RD signal,
as outlined in the Parallel Interface section, allowing the use of
the three LSBs of the address bus to select the channel address.
As shown in Figure 30, only Address Bit A3 to Address Bit A15
are address decoded, allowing A0 to A2 to be changed according to
desired channel selection without affecting chip selection.
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