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參數(shù)資料
| 型號： | AD7827BRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT SAMPLING SRL 8SOIC |
| 產品變化通告： | AD7827 Series Discontinuation 18/Jul/2012 |
| 標準包裝： | 1,000 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 1M |
| 數(shù)據接口： | DSP，串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
–3–
REV. 0
AD7827
TIMING CHARACTERISTICS1, 2 (V
REFIN/REFOUT = 2.5 V, all specifications –40 C to +105 C, unless otherwise noted)
Parameter
5 V
10%
3 V
10%
Units
Conditions/Comments
tCONVERT
420
ns max
Conversion Time.
t1
20
ns min
Minimum
CONVST Pulsewidth.
t2
tCONVERT+t3
ns min
Falling edge of
CONVST to falling edge of RFS.
tCONVERT+t3+t7+t8
ns max
t3
3
14
18
ns max
Rising edge of SCLK to falling edge of RFS.
t4
14
18
ns max
Rising edge of SCLK to rising edge of RFS.
t5
3
20
ns max
Rising edge of SCLK to high impedance disabled.
t6
3
14
18
ns max
Rising edge of SCLK to DOUT valid delay.
t7
25
ns min
Minimum high SCLK pulse duration.
t8
25
ns min
Minimum low SCLK pulse duration.
t9
4
20
ns min
Bus relinquish time after SCLK falling edge.
35
ns max
t10
20
ns max
Maximum delay from falling edge
CONVST to rising edge RFS if
RFS reset by
CONVST.
t11
30
ns min
Minimum time between end of serial read and next falling edge of
CONVST.
tPOWER-UP
11
s max
Power-up time from rising edge of
CONVST using external 2.5 V
reference.
tPOWER-UP
25
s max
Power-up time from rising edge of
CONVST using on-chip reference.
NOTES
1Sample tested to ensure compliance.
2See Figures 13, 14 and 15.
3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V with V
DD = 5 V ± 10% and time required for an
output to cross 0.4 V or 2.0 V with VDD = 3 V ± 10%.
4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 9, quoted in the timing characteristics is the true bus relinquish time of
the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
CL
50pF
TO
OUTPUT
PIN
IOL
IOH
200 A
+2.1V
Figure 1. Load Circuit for Digital Output Timing Specifications
Parameter
Version B
Units
Test Conditions/Comments
POWER SUPPLY
VDD
4.5
V min
5 V
± 10% For Specified Performance
5.5
V max
2.7
V min
3 V
± 10% For Specified Performance
3.3
V max
IDD
Normal Operation
10
mA max
8 mA Typically
Power-Down
1
A max
Logic Inputs = 0 V or VDD
Power Dissipation
VDD = 3 V
Normal Operation
30
mW max
Typically 24 mW
Power-Down
200 kSPS
9.58
mW max
1 MSPS
47.88
mW max
NOTES
1See Terminology section of this data sheet.
2Refer to the Analog Input section for an explanation of the Analog Input(s).
Specifications subject to change without notice.
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