參數(shù)資料
型號: AD7827
廠商: Analog Devices, Inc.
英文描述: 3 V/5 V, 1 MSPS, 8-Bit, Serial Interface Sampling ADC
中文描述: 3伏/ 5伏,1 MSPS的,8位,串行接口采樣ADC
文件頁數(shù): 6/12頁
文件大?。?/td> 185K
代理商: AD7827
AD7827
–6–
REV. 0
CIRCUIT DE SCRIPT ION
T he AD7827 consists of a track-and-hold amplifier followed by
a half-flash analog-to-digital converter. T his device uses a half-
flash conversion technique where one 4-bit flash ADC is used to
achieve an 8-bit result. T he 4-bit flash ADC contains a sampling
capacitor followed by 15 comparators that compare the unknown
input to a reference ladder to get a 4-bit result. T his first flash,
i.e., coarse conversion, provides the 4 MSBs. For a full 8-bit
reading to be realized, a second flash, i.e., a fine conversion,
must be performed to provide the 4 LSBs. T he 8-bit word is
then placed in the serial shift register.
Figures 2 and 3 below show simplified schematics of the ADC.
When the ADC starts a conversion, the track-and-hold goes into
hold mode and holds the analog input for 120 ns. T his is the
acquisition phase as shown in Figure 2 when Switch 2 is in
Position A. At the point when the track-and-hold returns to its
track mode, this signal is sampled by the sampling capacitor as
Switch 2 moves into Position B. T he first flash occurs at this
instant and is then followed by the second flash. T ypically the
first flash is complete after 100 ns, i.e., at 220 ns, while the end
REFERENCE
D
O
O
.
.
.
.
TCONTROL
LOGIC
HOLD
SW2
B
A
SAMPLING
R16
R15
R14
R13
R1
15
14
13
1
T/H
D
OUT
V
IN
Figure 2. ADC Acquisition Phase
REFERENCE
D
O
O
.
.
.
.
TIMING AND
CLOGIC
HOLD
SW2
B
A
SAMPLING
CAPACITOR
R16
R15
R14
R13
R1
15
14
13
1
T/H
D
OUT
V
IN
Figure 3. ADC Conversion Phase
of the second flash, and hence the 8-bit conversion result, is
available at 330 ns. As shown in Figure 4 the track-and-hold
returns to track mode after 120 ns, and so starts the next acqui-
sition before the end of the current conversion. Figure 6 shows
the ADC transfer function.
120ns
t
1
t
2
t
3
t
7
t
8
t
4
t
10
HOLD
HOLD
TRACK
TRACK
1
2
3
4
5
6
7
8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CONVST
RFS
SCLK
D
OUT
Figure 4. Track-and-Hold Timing
T Y PICAL CONNE CT ION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7827.
T he serial interface is implemented using three wires; the RFS is
a logic output and the serial clock is continuous. T he Receive
Frame Sync signal (RFS) idles high, the falling edge of
CONVST
initiates a conversion and the first rising edge of the serial clock
after the end of conversion causes the RFS signal to go low.
T his falling edge of RFS is used to drive the RFS on a micro-
processor—see Serial Interface section for more details. V
REF
is
connected to a voltage source such as the AD780, while V
DD
is
connected to a voltage source of 3 V
±
10% or 5 V
±
10%. Due
to the proximity of the
CONVST
and V
IN
pins, it is recom-
mended to use a 10 nF decoupling capacitor on V
IN
. When V
DD
is first connected the AD7827 powers up in a low current mode,
i.e., power-down. A rising edge on the
CONVST
pin will cause
the AD7827 to fully power up. For applications where power
consumption is of concern, the automatic power-down at the
end of a conversion should be used to improve power perfor-
mance. See the Power-Down Options section of this data sheet.
m
C/
m
P
0.1
m
F
10
m
F
2.5V
AD780
THREE-WIRE
SERIAL INTERFACE
0V TO 2.5V (V
DD
= 5V)
0V TO 2V (V
DD
= 3V)
INPUT
SUPPLY
+3V
6
10% OR
+5V
6
10%
SCLK
D
OUT
RFS
CONVST
V
DD
V
REF
V
IN
GND
AD7827
Figure 5. Typical Connection Diagram
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