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參數(shù)資料
| 型號(hào)： | AD7825BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel Sampling ADCs |
| 中文描述： | 4-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 215K |
| 代理商： | AD7825BR |
AD7822/AD7825/AD7829
TIMING CHARACTERISTICS
1, 2
–4–
REV. A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7822/AD7825/AD7829 features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Parameter 5 V
6
10%
3 V
6
10%
Unit
Conditions/Comments
t
1
t
2
t
3
t
4
420
20
30
110
70
10
0
0
30
10
5
20
10
15
200
25
1
420
20
30
110
70
10
0
0
30
20
5
20
10
15
200
25
1
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
μ
s typ
μ
s max
Conversion Time.
Minimum
CONVST
Pulsewidth.
Minimum time between the rising edge of
RD
and next falling edge of convert start.
EOC
Pulsewidth.
t
5
t
6
t
7
t
8
t
93
t
104
RD
rising edge to
EOC
pulse high.
CS
to
RD
setup time.
CS
to
RD
hold time.
Minimum
RD
Pulsewidth.
Data access time after
RD
low.
Bus relinquish time after
RD
high.
t
11
t
12
t
13
t
POWER UP
t
POWER UP
Address setup time before falling edge of
RD
.
Address hold time after falling edge of
RD
.
Minimum time between new channel selection and convert start.
Power-up time from rising edge of
CONVST
using on-chip reference.
Power-up time from rising edge of
CONVST
using external 2.5 V reference.
NOTES
1
Sample tested to ensure compliance.
2
See Figures 20, 21 and 22.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V with V
DD
= 5 V
±
10%, and time required for an out-
put to cross 0.4V or 2.0V with V
DD
= 3 V
±
10%.
4
Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
10
, quoted in the timing characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
*
(T
A
= +25
°
C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
Analog Input Voltage to AGND
V
IN1
to V
IN8
. . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to AGND . . . –0.3 V to V
DD
+ 0.3V
V
MID
Input Voltage to AGND . . . . . . . –0.3 V to V
DD
+ 0.3V
Digital Input Voltage to DGND . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40
°
C to +85
°
C
Storage Temperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150
°
C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105
°
C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . . 260
°
C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75
°
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220
°
C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 128
°
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
°
C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
*
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(V
REF IN/OUT
= 2.5 V. All specifications –40
8
C to +85
8
C unless otherwise noted)
WARNING!
ESD SENSITIVE DEVICE
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD7825BR-REEL | 制造商:Analog Devices 功能描述:ADC Single Semiflash 2Msps 8-bit Parallel 24-Pin SOIC W T/R |
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| AD7825BRU-REEL7 | 制造商:Analog Devices 功能描述:ADC Single Semiflash 2Msps 8-bit Parallel 24-Pin TSSOP T/R |
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