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參數(shù)資料
| 型號： | AD7810YNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SRL HS LP 8DIP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 350k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個偽差分，單極 |
AD7810
–7–
REV. B
When using the pseudo differential input scheme, the signal on
VIN– must not vary by more than a 1/2 LSB during the conver-
sion process. If the signal on VIN– varies during conversion, the
conversion result will be incorrect. For single-ended operation,
VIN– is always connected to AGND. Figure 9 shows the AD7810
pseudo differential input being used to make a unipolar dc cur-
rent measurement. A sense resistor is used to convert the current
to a voltage and the voltage, is applied to the differential input
as shown.
VDD
RSENSE
RL
VIN+
VIN–
AD7810
Figure 9. DC Current Measurement Scheme
DC Acquisition Time
The ADC starts a new acquisition phase at the end of a conver-
sion and ends on the falling edge of the CONVST signal. At the
end of a conversion there is a settling time associated with the
sampling circuit. This settling time lasts approximately 100 ns.
The analog signal on VIN+ is also being acquired during this
settling time; therefore, the minimum acquisition time needed is
approximately 100 ns.
Figure 10 shows the equivalent charging circuit for the sampling
capacitor when the ADC is in its acquisition phase. R2 repre-
sents the source impedance of a buffer amplifier or resistive
network; R1 is an internal multiplexer resistance and C1 is the
sampling capacitor.
C1
3.5pF
R1
125
VIN+
R2
Figure 10. Equivalent Sampling Circuit
During the acquisition phase, the sampling capacitor must be
charged to within a 1/2 LSB of its final value. The time it takes
to charge the sampling capacitor (tCHARGE) is given by the fol-
lowing formula:
tCHARGE = 7.6
× (R2 + 125 ) × 3.5 pF
For small values of source impedance, the settling time associated
with the sampling circuit (100 ns) is, in effect, the acquisition
time of the ADC. For example, with a source impedance (R2)
of 10
, the charge time for the sampling capacitor is approxi-
mately 4 ns. The charge time becomes significant for source
impedances of 2 k
and greater.
AC Acquisition Time
In ac applications it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of
the ADC. Large values of source impedance will cause the THD
to degrade at high throughput rates. In addition, better perfor-
mance can generally be achieved by using an external 1 nF
capacitor on VIN+.
ADC TRANSFER FUNCTION
The output coding of the AD7810 is straight binary. The
designed code transitions occur at successive integer LSB values
(i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/1024. The
ideal transfer characteristic for the AD7810 is shown in Figure
11 below.
000...010
000...001
000...000
ADC
CODE
0V
+VREF –1LSB
ANALOG INPUT
111...111
111...110
111...000
011...111
1LSB
1LSB = VREF/1024
Figure 11. Transfer Characteristic
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| AD7810YRMZ | 功能描述:IC ADC 10BIT SRL HS LP 8MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
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