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參數(shù)資料
| 型號： | AD7783BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 2CHAN R-R 16TSSOP |
| 標準包裝： | 1,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 19.79 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 3.9mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
–4–
AD7783
Limit at TMIN, TMAX
Parameter
(B Version)
Unit
Conditions/Comments
t1
30.5176
ms typ
Crystal Oscillator Period
tADC
50.54
ms typ
19.79 Hz Update Rate
t2
0
ns min
CS Falling Edge to DOUT Active
60
ns max
VDD = 4.75 V to 5.25 V
80
ns max
VDD = 2.7 V to 3.6 V
t3
2
tADC
ns typ
Channel Settling Time
t4
3
0
ns min
SCLK Active Edge to Data Valid Delay
4
60
ns max
VDD = 4.75 V to 5.25 V
80
ns max
VDD = 2.7 V to 3.6 V
t7
5
10
ns min
Bus Relinquish Time after
CS Inactive Edge
80
ns max
t8
0
ns min
CS Rising Edge to SCLK Inactive Edge Hold Time
t9
10
ns min
SCLK Inactive to DOUT High
80
ns max
Slave Mode Timing
t5
100
ns min
SCLK High Pulse Width
t6
100
ns min
SCLK Low Pulse Width
Master Mode Timing
t5
t1/2
ms typ
SCLK High Pulse Width
t6
t1/2
ms typ
SCLK Low Pulse Width
t10
t1/2
ms min
DOUT Low to First SCLK Active Edge
4
3t1/2
ms max
NOTES
1Sample tested during initial release to ensure compliance. All input signals are specified with t
R = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2See Figure 2.
3These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL or VOH limits.
4SCLK active edge is falling edge of SCLK.
5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means the times quoted in the timing characteristics are the true bus relin-
quish times of the part and as such are independent of external bus loading capacitances.
TIMING CHARACTERISTICS1, 2 (V
DD = 2.7 V to 3.6 V or VDD = 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz;
Input Logic 0 = 0 V, Logic 1 = VDD, unless otherwise noted.)
TO OUTPUT
PIN
50pF
ISINK (1.6mA WITH VDD = 5V
100 A WITH VDD = 3V)
1.6V
ISOURCE( 200 A WITH VDD = 5V
100 A WITH VDD = 3V)
Figure 1. Load Circuit for Timing Characterization
REV. C
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