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參數(shù)資料
| 型號(hào)： | AD7767BRUZ-2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | ADC 24BIT 32KSPS SAR 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 32k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 18mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極 |
| 產(chǎn)品目錄頁面： | 779 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7767EDZ-ND - BOARD EVAL AD7767 128KSPS 108DB EVAL-AD7767-1EDZ-ND - BOARD EVAL AD7767-1 64KSPS 111DB |
AD7767
Rev. C | Page 18 of
24
DAISY CHAINING
Daisy chaining devices allows numerous devices to use the same
digital interface lines by cascading the outputs of multiple ADCs
on a single data line. This feature is especially useful for reduc-
ing component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clocking a
shift register where data is clocked on the falling edge of SCLK.
The block diagram in Figure 36 shows how devices must be
connected to achieve daisy-chain functionality. The scheme
shown operates by passing the output data of the SDO pin of an
AD7767 device to the SDI input of the next AD7767 device in
the chain. The data then continues through the chain until it is
clocked onto the SDO pin of the first device in the chain.
READING DATA IN DAISY-CHAIN MODE
An example of a daisy chain of four AD7767 devices is shown in
output of the AD7767 labeled A is the output of the full daisy
chain. The last device in the chain (the AD7767 labeled D) has
its serial data input (SDI) pin connected to ground. All the
devices in the chain must use common MCLK, SCLK, CS, and
SYNC/PD signals.
To enable the daisy-chain conversion process, apply a common
SYNC/PD pulse to all devices, synchronizing all the devices in
the chain (see the
section).
After applying a SYNC/PD pulse to all the devices, there is a
delay (as listed in
) before valid conversion data appears
at the output of the chain of devices. As shown in
, the
first conversion result is output from the AD7767 device labeled
A. This 24-bit conversion result is followed by the conversion
results from the devices labeled B, C, and D, respectively, with
all conversion results output in an MSB-first sequence. The
stream of conversion results is clocked through each device in
the chain and is eventually clocked onto the SDO pin of the
AD7767 device labeled A. The conversion results of all the
devices in the chain must be clocked onto the SDO pin of the
final device in the chain while its
DRDY signal is active low.
This is illustrated in the examples shown (
and
),
where the conversion results from the devices labeled A, B, C,
and D are clocked onto SDO (A) during the time between the
falling edge of
DRDY (A) and the rising edge of DRDY (A).
CHOOSING THE SCLK FREQUENCY
As shown in Figure 37, the number of SCLK falling edges that
occur during the period when DRDY (A) is active low must
match the number of devices in the chain multiplied by 24 (the
number of bits that must be clocked through onto SDO (A) for
each device).
The period of SCLK (tSCLK) required for a known daisy-chain
length using a known common MCLK frequency must,
therefore, be established in advance. Note that the maximum
In the case where CS is tied logic low,
×
≤
K
t
READ
SCLK
24
(1)
where:
K
is the number of AD7767 devices in the chain.
tSCLK
is the period of the SCLK.
tREAD
equals tDRDY t5.
In the case where CS is used in the daisy-chain interface,
(
) (
)
×
+
≤
K
t
13
7
6
READ
SCLK
24
(2)
where:
K
is the number of AD7767 devices in the chain.
tSCLK
is the period of the SCLK.
tREAD
equals tDRDY t5.
Note that the maximum value of SCLK is governed by t8 and is
specified in the Timing Specifications table for different VDRIVE
voltages.
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