參數(shù)資料
型號: AD7764BRUZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 22/33頁
文件大小: 0K
描述: IC ADC 24BIT S/D 312KSPS 28TSSOP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 24
采樣率(每秒): 312k
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 371mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極;1 個差分,雙極
AD7764
Rev. A | Page 28 of 32
USING THE AD7764
Step1 through Step 5 detail the sequence for powering up and
using the AD7764.
1. Apply power to the device.
2. Apply the MCLK signal.
3. Take RESET low for a minimum of one MCLK cycle,
preferably synchronous to the falling MCLK edge. If
multiple parts are to be synchronized, apply a common
4. Wait a minimum of two MCLK cycles after
RESET to all devices.
RESET
5. If multiple parts are being synchronized, a
is
released.
SYNC pulse
must be applied to the parts, preferably synchronous with
the MCLK rising edge. In the case where devices are not
being synchronized, no SYNC pulse is required; a logic
high signal should simply be applied to the SYNC
When applying the
pin.
SYNC
The issue of a
pulse,
SYNC
Ensure that the
pulse to the device must not
coincide with a write to the device.
SYNC
Data can then be read from the device using the default gain
and overrange threshold values. The conversion data read is not
valid, however, until the settling time of the filter has elapsed.
Once this has occurred, the FILTER-SETTLE status bit is set,
indicating that the data is valid.
Values for gain and overrange thresholds can be written to or
read from the respective registers at this stage.
pulse is taken low for a
minimum of four MCLK periods.
BIAS RESISTOR SELECTION
The AD7764 requires a resistor to be connected between the
RBIAS and AGNDx pins. The resistor value should be selected to
give a current of 25 A through the resistor to ground. For a
4.096 V reference voltage, the correct resistor value is 160 k.
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